Method of manufacturing semiconductor device and semiconductor device

Patent metadata

Field	Value
Publication number	US-2016268290-A1
Application number	US-201514741621-A
Country	US
Kind code	A1
Filing date	Jun 17, 2015
Priority date	Mar 11, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

In a method of manufacturing a semiconductor device of an embodiment, first and second mask patterns are formed on a stacked body formed on a semiconductor substrate. Then, a first step-like pattern and a first dummy pattern are formed from the stacked body. When the second mask pattern becomes smaller than a predetermined size, a resist is applied, and a third mask pattern using the resist is formed. Then, a second step-like pattern and a second dummy pattern are formed from the stacked body.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device comprising:
forming, on a semiconductor substrate, a stacked body in which a plurality of films is stacked; forming a first mask pattern on the stacked body; forming a second mask pattern on the stacked body; repeating first processing including processing of etching the stacked body, and processing of slimming the second mask pattern; forming a first step-like pattern in which a lower side than the second mask pattern is remained, and a first dummy pattern in which a lower side than the first mask pattern is remained, from the stacked body; removing the second mask pattern when the second mask pattern becomes smaller than a predetermined size; applying a resist on the semiconductor substrate; forming a third mask pattern using the resist on the stacked body; repeating second processing including processing of etching the stacked body, and processing of slimming the third mask pattern; and forming a second step-like pattern in which a lower side than the first step-like pattern is remained, and a second dummy pattern in which a lower side than the first dummy pattern is remained, from the stacked body.

2 . The method of manufacturing a semiconductor device according to claim 1 , wherein
the stacked body is a body in which a first insulating layer used in formation of an electrode film, and a second insulating layer used in formation of a spacer film arranged between the electrode films are alternately stacked.

3 . The method of manufacturing a semiconductor device according to claim 1 , wherein
the first mask pattern is a dummy mask pattern formed in a region in which the stacked body is not used in formation of a memory cell and the first and second step-like patterns, the region being of an upper surface region of the stacked body.

4 . The method of manufacturing a semiconductor device according to claim 1 , wherein
the second mask pattern is a first resist pattern formed in a first region on the electrode film.

5 . The method of manufacturing a semiconductor device according to claim 1 , wherein
the third mask pattern is a second resist pattern formed in a second region on the electrode film.

6 . The method of manufacturing a semiconductor device according to claim 2 , wherein
the electrode films are formed in positions of the first insulating layers included in the first and second step-like patterns.

7 . The method of manufacturing a semiconductor device according to claim 6 , wherein
the first insulating layer is a silicon nitride.

8 . The method of manufacturing a semiconductor device according to claim 6 , wherein
the second insulating layer is a silicon oxide.

9 . The method of manufacturing a semiconductor device according to claim 3 , wherein
the dummy mask pattern is amorphous silicon or polysilicon.

10 . The method of manufacturing a semiconductor device according to claim 1 , comprising:
forming an interlayer insulating film on the semiconductor substrate after the second step-like pattern is formed; etching back and flattening the dummy mask pattern and the interlayer insulating film when the dummy mask pattern is remained; and etching back and flattening the interlayer insulating film when the dummy mask pattern is not remained.

11 . The method of manufacturing a semiconductor device according to claim 1 , wherein
there is a plurality of cell regions in which the memory cells are arranged, on one layer, the cell regions are divided by a groove pattern, and the first and second dummy patterns are formed in a region not overlapping with the groove pattern.

12 . The method of manufacturing a semiconductor device according to claim 2 , comprising:
forming a cap layer on the first dummy pattern; performing wet etching from the cap layer; making the first insulating layers remain included in the first and second dummy patterns; and removing the first insulating layers included in the first and second step-like patterns.

13 . The method of manufacturing a semiconductor device according to claim 12 , wherein
a metal film is formed in a region from which the first insulating layer is removed and becomes the electrode film.

14 . The method of manufacturing a semiconductor device according to claim 1 , wherein
the first mask pattern of when the etching to the stacked body is started has a film thickness that is remained after the second mask pattern is etched a plurality of times.

15 . A semiconductor device comprising:
memory cells arranged on a semiconductor substrate in a three-dimensional manner; electrode films formed in a step-like manner and connected to the memory cells; and a dummy pattern having a predetermined height and arranged in a region where the electrode films are not formed.

16 . The semiconductor device according to claim 15 , wherein
the dummy pattern includes a first insulating layer and a second insulating layer, a third insulating layer is formed between the electrode film formed on a first layer of the step-like electrode films, and the electrode film formed on a second layer of the step-like electrode films, and the second insulating layer and the third insulating layer are formed of a same member having a same film thickness.

17 . The semiconductor device according to claim 16 , wherein
the second insulating layer and the third insulating layer are arranged in positions of a same height.

18 . The semiconductor device according to claim 16 , wherein
the first insulating layer is a silicon nitride.

19 . The semiconductor device according to claim 16 , wherein
the second insulating layer is a silicon oxide.

20 . The semiconductor device according to claim 15 , wherein
the dummy pattern includes a first insulating layer and a second insulating layer, a fourth insulating layer is arranged in a region where the memory cells are arranged, and the second insulating layer and the fourth insulating layer are formed of a same member having a same film thickness.

Assignees

• Toshiba Kk

Inventors

• Matsunaga Yosuke
• Kuniya Takuji

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/50 Primary

  characterised by the boundary region between the core and peripheral circuit regions · CPC title