Technologies for low-power standby display refresh

Patent metadata

Field	Value
Publication number	US-2016267883-A1
Application number	US-201514644767-A
Country	US
Kind code	A1
Filing date	Mar 11, 2015
Priority date	Mar 11, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.

First claim

1 . A computing device for low-power display refresh, the computing device comprising:
a display driver module to determine whether a display image stored in a system memory of the computing device is static; a power management module to (i) enter a low-power display refresh standby mode in response to a determination that the display image is static and (ii) power down one or more components of a processor of the computing device in response to an entrance to the low-power display refresh standby mode; and a standby display module to (i) retrieve, by a display controller of the processor, image data of the display image from a display buffer in the system memory in response to the entrance of the low-power display refresh standby mode and (ii) output, by the display controller, the image data to a display of the computing device.

2 . The computing device of claim 1 , wherein the one or more components of the processor comprises a processor core.

3 . The computing device of claim 1 , wherein the one or more components of the processor comprises one or more banks of the system memory, wherein the one or more banks of the system memory do not include the display buffer.

4 . The computing device of claim 1 , wherein the one or more components of the processor comprises an input/output (I/O) fabric of the processor.

5 . The computing device of claim 1 , wherein:
to retrieve the image data from the display buffer in the system memory further comprises to store the image data in an internal buffer of the display controller; and to output the image data to the display comprises to output the image data from the internal buffer of the display controller.

6 . The computing device of claim 5 , wherein the power management module is further to:
determine whether the internal buffer of the display controller is full in response to retrieval of the image data; and power down one or more additional components of the processor in response to a determination that the internal buffer of the display controller is full.

7 . The computing device of claim 6 , wherein the one or more additional components of the processor comprises a bank of the system memory that includes the display buffer.

8 . The computing device of claim 7 , wherein:
to retrieve the image data from the display buffer in the system memory comprises to access, by the display controller, the display buffer in the system memory via a system-on-a-chip (SoC) transaction router of the processor; and the one or more additional components of the processor comprises the SoC transaction router.

9 . The computing device of claim 6 , wherein the power management module is further to:
determine whether the internal buffer of the display controller is below a predefined threshold level in response to powering down of the one or more additional components of the processor; and power on the one or more additional components of the computing device in response to a determination that the internal buffer of the display controller is below the predefined threshold level; wherein to retrieve the image data from the display buffer in the system memory comprises to retrieve the image data from the display buffer in the system memory in response to the determination that the internal buffer of the display controller is below the predefined threshold level.

10 . A method for low-power display refresh, the method comprising:
determining, by a computing device, whether a display image stored in a system memory of the computing device is static; entering, by the computing device, a low-power display refresh standby mode in response to determining that the display image is static; powering down, by the computing device, one or more components of a processor of the computing device in response to entering the low-power display refresh standby mode; retrieving, by a display controller of the processor of the computing device, image data of the display image from a display buffer in the system memory in response to entering the low-power display refresh standby mode; and outputting, by the display controller, the image data to a display of the computing device.

11 . The method of claim 10 , wherein powering down the one or more components of the processor comprises powering down one or more banks of the system memory, wherein the one or more banks of the system memory do not include the display buffer.

12 . The method of claim 10 , wherein:
retrieving the image data from the display buffer in the system memory further comprises storing the image data in an internal buffer of the display controller; and outputting the image data to the display comprises outputting the image data from the internal buffer of the display controller.

13 . The method of claim 12 , further comprising:
determining, by the computing device, whether the internal buffer of the display controller is full in response to retrieving the image data; and powering down, by the computing device, one or more additional components of the processor in response to determining the internal buffer of the display controller is full.

14 . The method of claim 13 , wherein powering down the one or more additional components of the processor comprises powering down a bank of the system memory that includes the display buffer.

15 . The method of claim 14 , wherein:
retrieving the image data from the display buffer in the system memory comprises accessing, by the display controller, the display buffer in the system memory via a system-on-a-chip (SoC) transaction router of the processor; and powering down the one or more additional components of the processor comprises powering down the SoC transaction router.

16 . The method of claim 13 , further comprising:
determining, by the computing device, whether the internal buffer of the display controller is below a predefined threshold level in response to powering down the one or more additional components of the processor; and powering on, by the computing device, the one or more additional components of the computing device in response to determining that the internal buffer of the display controller is below the predefined threshold level; wherein retrieving the image data from the display buffer in the system memory comprises retrieving the image data from the display buffer in the system memory in response to determining that the internal buffer of the display controller is below the predefined threshold level.

17 . One or more computer-readable storage media comprising a plurality of instructions that in response to being executed cause a computing device to:
determine whether a display image stored in a system memory of the computing device is static; enter a low-power display refresh standby mode in response to determining that the display image is static; power down one or more components of a processor of the computing device in response to entering the low-power display refresh standby mode; retrieve, by a display controller of the processor of the computing device, image data of the display image from a display buffer in the system memory in response to entering the low-power display refresh standby mode; and output, by the display controller, the image data to a display of the computing device.

18 . The one or more computer-readable storage media of claim 17 , wherein to power down the one or more components of the processor comprises to power down one or more banks of the system memory, wherein the one or more banks of the system memory do not include the display bu

Assignees

• Intel Corp

Inventors

• Bibikar Vasudev
• Poornachandran Rajesh
• Durg Ajaya V
• Shah Arpit
• Sabbavarapu Anil K
• Kerkiz Nabil F
• Le Quang T
• Pinto Ryan R
• Rajesh Moorthy
• Bish James A
• Sridharan Ranjani

Classifications

• G09G5/001

  Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor · CPC title

• G09G2310/04

  Partial updating of the display screen · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G5/363 Primary

  Graphics controllers · CPC title

• G09G5/395

  Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen (G09G5/399 takes precedence) · CPC title