Methods and apparatus for equalization of a high speed serial bus

Patent metadata

Field	Value
Publication number	US-2016267044-A1
Application number	US-201514641170-A
Country	US
Kind code	A1
Filing date	Mar 6, 2015
Priority date	Mar 6, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

Methods and apparatus for equalization of a high speed serial bus. Various aspects of the present disclosure are directed to a well-tuned passive equalization circuit for use with high frequency differential signals that suffer from e.g., impedance mismatches, impedance discontinuities (e.g., connectors, etc.). In one embodiment, a shunting circuit is inserted between the differential terminals of a Universal Serial Bus (USB) cable, connector, etc. The shunting circuit is configured to “open” at low frequencies to enable Full Speed (FS) enumeration, while also providing sufficiently high impedance at high frequencies to enable High Speed (HS) operation. In one such implementation, the shunting circuit includes a tuned resistor, capacitor, inductor, and switch element arranged in series.

First claim

What is claimed is:

1 . A signal conditioning apparatus, comprising:
a first cable interface comprising a differential pair; a second cable interface comprising the differential pair; wherein the differential pair comprises a positive and a negative terminal that are coupled via a shunting circuit; and wherein the shunting circuit is configured to present a high impedance between the positive and negative terminals at a first frequency.

2 . The signal conditioning apparatus of claim 1 , wherein the shunting circuit is configured to present a high impedance between the positive and negative terminals at a second frequency different than the first.

3 . The signal conditioning apparatus of claim 1 , wherein the shunting circuit additionally comprises a switch element configured to open and close the shunting circuit.

4 . The signal conditioning apparatus of claim 3 , wherein the switch element is configured to open the shunting circuit during a first operational mode and close the shunting circuit during a second operational mode.

5 . The signal conditioning apparatus of claim 1 , wherein the shunting circuit is configured to flatten an attenuation over an increased frequency range.

6 . The signal conditioning apparatus of claim 5 , wherein the attenuation does not exceed 3 decibels (dB) over the increased frequency range of 300 Megahertz (MHz)

7 . The signal conditioning apparatus of claim 6 , wherein the differential pair comprises Universal Serial Bus (USB) D+ 0 and D− terminals.

8 . A signal conditioning apparatus, comprising:
a differential pair that comprises a positive and a negative terminal that are coupled via a shunting circuit; wherein the shunting circuit comprises at least a switch element; and wherein the shunting circuit is configured to alter a frequency response of the differential pair for at least one mode of operation.

9 . The signal conditioning apparatus of claim 8 , wherein the alteration comprises an increase in an insertion loss.

10 . The signal conditioning apparatus of claim 8 , wherein the alteration comprises a flatter frequency response.

11 . The signal conditioning apparatus of claim 10 , wherein the flatter frequency response includes a range of frequencies from direct current (DC) to 300 Megahertz (MHz).

12 . The signal conditioning apparatus of claim 11 , wherein the shunting circuit comprises a resistor, an inductor and a capacitor.

13 . The signal conditioning apparatus of claim 12 , wherein the resistor, the inductor, and the capacitor are connected in series between the positive and negative terminal.

14 . The signal conditioning apparatus of claim 12 , wherein the capacitor is selected to enable single ended signaling via the differential pair.

15 . A method for equalizing a high speed serial bus, comprising:
determining the high speed serial bus configuration; selecting one or more tuning considerations; selecting a shunting impedance from one or more possible shunting impedances; and enabling the selected shunting impedance.

16 . The method of claim 15 , wherein the act of determining the high speed serial bus configuration comprises discovering one or more devices attached to the high speed serial bus.

17 . The method of claim 15 , wherein the act of determining the high speed serial bus configuration comprises determining one or more operational modes.

18 . The method of claim 17 , wherein the one or more tuning considerations comprises flattening a frequency response corresponding to at least one of the one or more operational modes.

19 . The method of claim 17 , wherein the one or more tuning considerations comprises increasing an insertion loss corresponding to at least one of the one or more operational modes.

20 . The method of claim 19 , wherein the increased insertion loss enables a higher transmit power setting.

Assignees

• Apple Inc

Inventors

• Wu Songping
• Yang Zhiping
• Kalinichev Kirill
• Nayman Greg
• Beloev Georgi

Classifications

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title