Mapping virtual memory pages to physical memory pages

Patent metadata

Field	Value
Publication number	US-2016267015-A1
Application number	US-201315031181-A
Country	US
Kind code	A1
Filing date	Oct 29, 2013
Priority date	Oct 29, 2013
Publication date	Sep 15, 2016
Grant date	—

Abstract

A method for mapping virtual memory pages to physical memory pages is described. The method includes receiving a mapping of a virtual memory page to multiple physical memory pages, detecting a request for a transaction to be performed on data contained in the multiple physical memory pages, in which the transaction includes a number of data updates, determining which of the number of multiple physical memory pages contains a latest version of the data to be updated by the transaction, updating a physical memory page by performing the transaction within a physical memory page among the multiple physical memory pages that does not contain the latest version of the data, and updating an indication of which of the physical memory pages contains the latest version of the data pertaining to the transaction.

First claim

What is claimed is:

1 . A method for mapping virtual memory pages to physical memory pages, comprising:
receiving a mapping of a virtual memory page to multiple physical memory pages; detecting a request for a transaction to be performed on data contained in the multiple physical memory pages, in which a transaction comprises a number of data updates; determining which of the multiple physical memory pages contains a latest version of a portion of the data to be updated by the transaction; updating a physical memory page by performing the transaction within a physical memory page among the multiple physical memory pages that does not contain the latest version of the data; and updating an indication of which of the physical memory pages contains the latest version of the data pertaining to the transaction.

2 . The method of claim 1 , in which the indication is a version indicator table that indicates which of the multiple physical memory pages contains the latest version of the data for the current transaction.

3 . The method of claim 2 , further comprising redirecting a request for a transaction based on the update to the version indicator table.

4 . The method of claim 1 , in which a portion of a number of virtual memory pages are mapped to a physical memory location, in which the physical memory location comprises a master physical memory page and a shadow physical memory page for the number of virtual memory pages.

5 . The method of claim 1 , further comprising undoing a number of data updates when the transaction fails, the transaction is aborted, a system fails, or combinations thereof.

6 . The method of claim 1 , further comprising initializing a number of shadow physical memory pages of the multiple physical memory pages, in which initializing includes copying data from a master physical memory page to the number of shadow physical memory pages.

7 . The method of claim 6 , in which a number of shadow physical memory pages are initialized while data updates are being performed on other pages of the multiple physical memory pages.

8 . The method of claim 1 , further comprising receiving an indication of transaction boundaries.

9 . A system for mapping virtual memory pages to physical memory pages, comprising:
a processor; memory communicatively coupled to the processor; and a version controller, the version controller comprising:
a page descriptor module to receive a mapping of a virtual memory page to multiple physical memory pages;
a version indicator table to indicate which of the multiple physical memory pages contains a latest version of data for the current transaction represented by the virtual memory page;
a request buffer to perform a number of updates on one of the multiple physical memory pages; and
a table update module to update the version indicator table after one of the multiple physical memory pages has been updated.

10 . The system of claim 9 , in which the memory is non-volatile memory.

11 . The system of claim 9 , in which the version controller is located on the memory.

12 . The system of claim 9 , in which the version controller is located on the processor.

13 . The system of claim 9 , further comprising an address calculator to redirect a request for a transaction based on the version indicator table and the mapping.

14 . The system of claim 9 , in which the page to which a number of updates are performed is a page that does not contain a latest version of the data.

15 . A computer program product for mapping virtual memory pages to physical memory pages, the computer program product comprising:
a computer readable storage medium comprising computer usable program code embodied therewith and executed by a processor to:
detect a number of updates to be performed on data contained in multiple physical memory pages;
identify a master page of the multiple physical memory pages, in which the master page contains the latest version of the data;
perform the data updates on a shadow page, in which a shadow page is a page of the multiple physical memory pages that does not contain the latest version of the data; and
update an indication of which of the multiple physical memory pages contains the latest version of the data.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Li Sheng
• Zhao Jishen
• Chang Jichuan
• Ranganathan Parthasarathy
• Veitch Alistair
• Lim Kevin T

Classifications

• G06F12/10 Primary

  Address translation · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F2212/1041

  Resource optimization · CPC title

• G06F2212/152

  Virtualized environment, e.g. logically partitioned system · CPC title

• G06F12/109 Primary

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title