Array substrate, display panel and display apparatus

Patent metadata

Field	Value
Publication number	US-2016266431-A1
Application number	US-201514769303-A
Country	US
Kind code	A1
Filing date	Apr 10, 2015
Priority date	Oct 27, 2014
Publication date	Sep 15, 2016
Grant date	—

Abstract

An array substrate, a display panel and a display apparatus are disclosed. The array substrate includes a plurality of gate lines ( 10; 50 ) and a plurality of data lines ( 30; 51 ), and pixel units arranged in an array. Each of the pixel units includes one pixel electrode ( 41; 42 ) and one thin film transistor, the data line ( 30; 51 ) serve as a source electrode ( 31; 311 ) of the thin film transistor, the gate line ( 10; 50 ) serve as a gate electrode ( 11 ) of the thin film transistor, and a drain electrode ( 32; 321; 322 ) of the thin film transistor is electrically connected to the pixel electrode ( 41; 42 ), at least one of the gate lines ( 10; 50 ) and the data lines ( 30; 51 ) has a recess ( 363; 364 ) provided thereon aligned with a spacer for fixing. With the recess ( 363; 364 ), the post spacer is prevented from moving to affect the display region when the substrate is bent and deformed under an external pressure.

First claim

1 . An array substrate, comprising: a plurality of gate lines and a plurality of data lines, pixel units that are provided on the array substrate and arranged in an array, wherein,
each of the pixel units includes a pixel electrode and a thin film transistor, one of the data lines serves as a source electrode of the thin film transistor, one of the gate lines serves as a gate electrode of the thin film transistor, a drain electrode of the thin film transistor is electrically connected to the pixel electrode, and a recess configured for fixing a spacer and disposed opposite to the spacer is provided on at least one of the gate line and the data line.

2 . The array substrate according to claim 1 , wherein at least two recesses are provided on at least one of the gate line and the data line.

3 . The array substrate according to claim 2 , wherein two recesses are provided on at least one of the gate line and the data line, and the two recesses are provided on the gate line or the data line.

4 . The array substrate according to claim 2 , wherein two recesses are provided on at least one of the gate line and the data line, one of the two recesses is provided on the gate line, and the other of the two recesses is provided on the data line.

5 . The array substrate according to claim 2 , wherein the recesses include a circular recess and/or a rectangular recess.

6 . The array substrate according to claim 2 , wherein the recesses include a polygonal recess.

7 . The array substrate according to claim 3 , wherein the two recesses have different depths.

8 . The array substrate according to claim 3 , wherein one of the two recesses is provided with the pixel electrode therein.

9 . The array substrate according to claim 1 , wherein the drain electrode is electrically connected to the pixel electrode through a via hole, or the pixel electrode is directly taped to the drain electrode.

10 . The array substrate according to claim 9 , wherein the recess and the via hole are in a same layer.

11 . A display panel, comprising the array substrate according to claim 1 .

12 . A display apparatus, comprising the display panel according to claim 11 .

13 . The display apparatus according to claim 12 , wherein, the display apparatus is a liquid crystal display apparatus.

14 . The array substrate according to claim 3 , wherein the recesses include a circular recess and/or a rectangular recess.

15 . The array substrate according to claim 3 , wherein the recesses include a polygonal recess.

16 . The array substrate according to claim 4 , wherein the two recesses have different depths.

17 . The array substrate according to claim 4 , wherein one of the two recesses is provided with the pixel electrode therein.

18 . The array substrate according to claim 7 , wherein one of the two recesses is provided with the pixel electrode therein.

19 . The array substrate according to claim 2 , wherein the drain electrode is electrically connected to the pixel electrode through a via hole, or the pixel electrode is directly taped to the drain electrode.

20 . The display panel according to claim 11 , wherein at least two recesses are provided on at least one of the gate line and the data line.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Li Wenbo
• Li Pan
• Xian Jianbo
• Cheng Hongfei

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10P14/3454

  Amorphous · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title