Polarizer, method of manufacturing the polarizer and display panel having the polarizer

US2016266295A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016266295-A1
Application numberUS-201514846471-A
CountryUS
Kind codeA1
Filing dateSep 4, 2015
Priority dateMar 10, 2015
Publication dateSep 15, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

A method of manufacturing a polarizer includes forming a first layer on a base substrate, forming a first partition wall layer on the first layer, forming a second partition wall layer on the first partition wall, forming a plurality of first partition wall patterns and a plurality of second partition walls disposed on the first partition wall patterns by etching the first partition wall and the second partition wall at the same time, forming a block copolymer layer on the first layer on which the plurality of first partition wall patterns are formed, forming a plurality of fine patterns from the block copolymer layer, and patterning the first layer using the fine patterns and the second partition wall patterns as a mask.

First claim

Opening claim text (preview).

What is claimed is: 1 . A polarizer, comprising: a base substrate; a plurality of partition wall patterns disposed on the base substrate and spaced apart from each other; and a plurality of wire grid patterns disposed on the base substrate and disposed between the partition wall patterns, wherein the wire grid patterns comprise a plurality of wire grids, and each of the plurality of partition wall patterns has a width larger than a width of the each of the plurality of wire grids. 2 . The polarizer of claim 1 , wherein the plurality of partition wall patterns and the plurality of wire grid patterns are formed at a same layer. 3 . The polarizer of claim 1 , wherein a distance between the adjacent partition wall patterns is about 2 um (micrometer) to 4 um. 4 . The polarizer of claim 1 , wherein each of the plurality of the partition wall pattern is about 1.25 um to 2.5 um wide, and each of the plurality of the wire grids is about 45 nm to 65 nm wide. 5 . A method of manufacturing a polarizer, comprising: forming a first layer on a base substrate; forming a first partition wall layer on the first layer; forming a second partition wall layer on the first partition wall; forming a plurality of first partition wall patterns and a plurality of second partition wall patterns disposed on the first partition wall patterns by etching the first partition wall and the second partition wall at the same time; forming a block copolymer layer on the first layer on which the plurality of first partition wall patterns are formed; forming a plurality of fine patterns from the block copolymer layer; and patterning the first layer using the fine pattern as a mask. 6 . The method of claim 5 , wherein the first partition wall layer comprises a material having relatively higher etch selectivity in comparison with the second partition wall layer. 7 . The method of claim 6 , wherein the first partition wall layer comprises silicon nitride, and the second partition wall layer comprises silicon oxide. 8 . The method of claim 5 , wherein the block copolymer layer comprises first polymer blocks and second polymer blocks which are in covalent bond with 1:1 volume ratio. 9 . The method of claim 8 , wherein the step of forming the plurality of fine patterns further comprises: forming the plurality of fine patterns having a plurality of first blocks and a plurality of second blocks which have monomer units, wherein the plurality of second blocks consist of monomer unit having components different from components of monomer unit of the plurality of first blocks, and wherein the plurality of first blocks and the plurality of second blocks are formed by rearrangement of components of the block copolymer layer through a phase separation. 10 . The method of claim 5 , wherein each of the plurality of second partition wall patterns is more than twice wider than each of the plurality of first partition wall patterns. 11 . The method of claim 10 , wherein each of the plurality of first partition wall patterns is about 0.5 to 1 um (micrometer) wide, and each of the plurality of second partition wall pattern is about 1.25 to 2.5 um wide. 12 . The method of claim 5 , further comprising: forming a second layer on the first layer before forming the plurality of first partition wall layers. 13 . The method of claim 5 , further comprising: forming a plurality of wire grid patterns corresponding to the plurality of fine patterns and a plurality of partition wall patterns corresponding to the plurality of second partition wall patterns by patterning the first layer. 14 . The method of claim 13 , wherein a width of each of the plurality of partition wall patterns is substantially same as that of each of the plurality of second partition wall patterns. 15 . The method of claim 5 , wherein a cross-section of each of the plurality of first partition wall patterns and each of the plurality of second partition wall patterns is trapezoid having an upper side longer than a lower side. 16 . The method of claim 5 , wherein a cross-section of each of the plurality of first partition wall patterns and each of the plurality of second partition wall patterns is a shape that has upper side longer than a lower side, and has a curved side. 17 . The method of claim 5 , wherein forming the plurality of first partition wall patterns and the plurality of second partition wall patterns further comprises: forming a third later on the second layer; forming a fifth layer on the second layer; forming a photoresist pattern on the fifth layer; forming a fifth layer pattern by etching the fifth layer using the photoresist pattern as a mask; forming a sixth layer on the fifth layer pattern and the third layer; forming a sixth layer pattern by etching the sixth layer; removing the fifth layer pattern; forming a third layer pattern by etching the third layer using the sixth layer pattern as a mask; and forming the plurality of first partition wall patterns and the plurality of second partition wall patterns by etching the first partition wall and the second partition wall using the third layer pattern as a mask at the same time. 18 . A display panel, comprising: a first substrate comprising a base substrate and a polarizer disposed on the base substrate; a second substrate facing the first substrate; and a liquid crystal layer disposed between the first substrate and the second substrate, wherein the polarizer comprises: a plurality of partition wall patterns disposed on the base substrate and spaced apart from each other; and a wire grid pattern disposed on the base substrate and disposed between the partition wall patterns, wherein the wire grid pattern comprises a plurality of wire grids, and each of the partition wall patterns has a width larger than a width of the wire grid. 19 . The display panel of claim 18 , wherein the plurality of partition wall patterns and the wire grid pattern are formed of a same layer. 20 . The display panel of claim 19 , wherein a distance between the adjacent partition wall patterns is about 2 um (micrometer) to 4 um, and a width of each of the plurality of the partition wall patterns is about 1.25 um to 2.5 um.

Assignees

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Classifications

  • the removal being a selective chemical etching step, e.g. selective dry etching through a mask · CPC title

  • Process specially adapted to improve the resolution of the mask · CPC title

  • characterised by their composition, e.g. multilayer masks or materials · CPC title

  • Chemical etching · CPC title

  • by chemical means · CPC title

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What does patent US2016266295A1 cover?
A method of manufacturing a polarizer includes forming a first layer on a base substrate, forming a first partition wall layer on the first layer, forming a second partition wall layer on the first partition wall, forming a plurality of first partition wall patterns and a plurality of second partition walls disposed on the first partition wall patterns by etching the first partition wall and th…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02B5/3058. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Sep 15 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).