System and Method for a Phase Detector

Patent metadata

Field	Value
Publication number	US-2016266185-A1
Application number	US-201615074429-A
Country	US
Kind code	A1
Filing date	Mar 18, 2016
Priority date	Feb 4, 2014
Publication date	Sep 15, 2016
Grant date	—

Abstract

In accordance with an embodiment, a method of detecting a phase difference between a first signal and a second signal include latching a state of the first signal using the second signal as a clock to produce a first latched signal, latching a state of the second signal using the first signal as a clock to produce a second latched signal summing the first latched signal and the second latched signal to produce an indication of whether the first signal is leading or lagging the second signal.

First claim

What is claimed is:

1 . A method of detecting a phase difference between a first signal and a second signal using a phase detector comprising a plurality of cascaded RF stages, each of the plurality of cascaded RF stages having a first RF amplifier and a second RF amplifier, wherein first RF amplifiers are cascaded with first RF amplifiers of successive RF stages and second RF amplifiers are cascaded with second RF amplifiers of successive RF stages, the method comprising:
receiving the first signal at an input of a first RF amplifier of a first RF stage; receiving the second signal an input of a second RF amplifier of the first RF stage; latching a state of the first signal using the second signal as a clock to produce a first latched signal, wherein latching the state of the first signal comprises using a first latch circuit having a first input coupled to an output of the first RF amplifier of a first RF stage and a second input coupled to an output of the second RF amplifier of the first RF stage; latching a state of the second signal using the first signal as a clock to produce a second latched signal, wherein latching the state of the second signal comprises using a second latch circuit having a first input coupled to an output of a second RF amplifier of a second RF stage, and a second input coupled to an output of a first RF amplifier of the second RF stage; and producing an indication of whether the first signal is leading or lagging the second signal, producing the indication comprising summing the first latched signal and the second latched signal.

2 . The method of claim 1 , wherein:
latching the state of the first signal using the second signal as a clock further comprises producing a third latched signal using a third latch circuit having a first input coupled to an output of a first RF amplifier of a third RF stage and a second input coupled to an output of a second RF amplifier of the third RF stage; latching the state of the second signal using the first signal as a clock further comprises producing a fourth latched signal using a fourth latch circuit having a first input coupled to an output of a first RF amplifier of a fourth RF stage and a second input coupled to an output of a second RF amplifier of the fourth RF stage; and producing the indication of whether the first signal is leading or lagging the second signal, further comprises summing the third latched signal and the fourth latched signal along with the first latched signal and the second latched signal.

3 . The method of claim 2 , further comprising inverting first latched signal and the third latched signal before the summing the third latched signal and the fourth latched signal along with the first latched signal and the second latched signal.

4 . The method of claim 2 , wherein:
an input of the first RF amplifier of the second RF stage is directly connected to the output of the first RF amplifier of the first RF stage; an input of the second RF amplifier of the second RF stage is directly connected to the output of the second RF amplifier of the first RF stage; an input of the first RF amplifier of the third RF stage is directly connected to the output of the first RF amplifier of the second RF stage; an input of the second RF amplifier of the third RF stage is directly connected to the output of the second RF amplifier of the second RF stage; an input of the first RF amplifier of the fourth RF stage is directly connected to the output of the first RF amplifier of the third RF stage; and an input of the second RF amplifier of the fourth RF stage is directly connected to the output of the second RF amplifier of the third RF stage.

5 . The method of claim 1 , wherein:
the first input of the first latch circuit is a data input and the second input of the first latch circuit a clock input; and the first input of the second latch circuit is a data input and the second input of the second latch circuit is a clock input.

6 . The method of claim 1 , wherein the first latch circuit is a gated latch and the second latch circuit is a gated latch.

7 . The method of claim 1 , wherein each of the plurality of cascaded RF stages form a logarithmic amplifier.

8 . The method of claim 1 , wherein summing the first latched signal and the second latched signal comprises low pass filtering the first latched signal and the second latched signal.

9 . The method of claim 8 , wherein low pass filtering comprises using a RC network.

10 . The method of claim 1 , further comprising providing the first signal and the second signal from outputs of a directional coupler.

11 . The method of claim 1 , wherein the plurality of cascaded RF stages, the first latch circuit and the second latch circuit have differential signal paths.

12 . An RF system comprising:
a directional coupler comprising an input port, an output port, a first measurement output and a second measurement output; and a phase detector circuit comprising
a first latch circuit having a first input coupled to the first measurement output of the directional coupler and a second input coupled to the second measurement output of the directional coupler,
a second latch circuit having a first input coupled to the second measurement output of the directional coupler and a second input coupled to the first measurement output of the directional coupler, and
a summing circuit having a first input coupled to an output of the first latch circuit and a second input coupled to output of the second latch circuit, wherein an output of the summing circuit indicates whether a signal at the first measurement output of the directional coupler is leading or lagging a signal at the second measurement output of the directional coupler.

13 . The RF system of claim 12 , wherein:
the first measurement output of the directional coupler comprises a voltage measurement output and the second measurement output of the directional coupler comprises a current measurement output.

14 . The RF system of claim 12 , wherein:
the first latch circuit is configured to pass a state from the first input of the first latch circuit to the output of the first latch circuit when the second input of the first latch circuit is in a first state, and to hold a state at the output of the first latch circuit when the second input of the first latch circuit is in a second state different from the first state; and the second latch circuit is configured to pass a state from the first input of the second latch circuit to the output of the second latch circuit when the second input of the second latch circuit is in the first state, and to hold a state at the output of the second latch circuit when the second input of the second latch circuit is in the second state.

15 . The RF system of claim 12 , further comprising:
a first logarithmic amplifier coupled between the first measurement output of the directional coupler and the phase detector circuit; and a second logarithmic amplifier coupled between the first measurement output of the directional coupler and the phase detector circuit.

16 . The RF system of claim 12 , further comprising:
an antenna port coupled to the output port of the directional coupler; and an antenna switch coupled to the input port of the directional coupler.

17 . The RF system of claim 16 , further comprising an antenna coupled to the antenna port.

18 . The RF system of claim 16 , further comprising an impedance tuner coupled in series with the directional coupler and the antenna port.

Assignees

• Infineon Technologies Ag

Inventors

• Solomko Valentyn

Classifications

• H03K5/26 Primary

  the characteristic being duration, interval, position, frequency, or sequence · CPC title

• H03D13/00

  Circuits for comparing the phase or frequency of two mutually-independent oscillations {(measuring phase G01R25/00; phase-discriminators with yes/no output G01R25/005)} · CPC title

• G01R25/005 Primary

  Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller, or for passing one of the input signals as output signal · CPC title

• G01R25/00

  Arrangements for measuring phase angle between a voltage and a current or between voltages or currents · CPC title

• H03D13/001

  in which a pulse counter is used followed by a conversion into an analog signal · CPC title