VDS Equalizer Offset Compensation for a Current Sense Circuit

Patent metadata

Field	Value
Publication number	US-2016266178-A1
Application number	US-201514838266-A
Country	US
Kind code	A1
Filing date	Aug 27, 2015
Priority date	Mar 12, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

A current sense circuit for a pass transistor is described. The current sense circuit comprises a sense transistor, a differential amplifier comprising a differential input and a differential output, and a differential difference amplifier, referred to as DD amplifier, comprising a main differential input, an auxiliary differential input and an output; wherein the differential output of the differential amplifier is coupled to the auxiliary differential input of the DD amplifier; wherein the output port of the pass transistor is coupled to a first port of the main differential input and wherein the output port of the sense transistor is coupled to a second port of the main differential input. The output of the DD amplifier is used to control a voltage drop across the sense transistor and the pass transistor.

First claim

What is claimed is:

1 ) A current sense circuit for a pass transistor, wherein the current sense circuit comprises,
a sense transistor having an input port that is coupled to an input port of the pass transistor and having a control port that is coupled to a control port of the pass transistor; a differential amplifier comprising a differential input and a differential output; wherein an output port of the pass transistor is coupled to a first port of the differential input and wherein an output port of the sense transistor is coupled to a second port of the differential input; and a differential difference amplifier, referred to as DD amplifier, comprising a main differential input, an auxiliary differential input and an output; wherein the differential output of the differential amplifier is coupled to the auxiliary differential input of the DD amplifier; wherein the output port of the pass transistor is coupled to a first port of the main differential input ( 204 ) and wherein the output port of the sense transistor ( 111 ) is coupled to a second port of the main differential input ( 204 ); wherein the output of the DD amplifier ( 201 ) is used to control a voltage drop across the sense transistor ( 111 ) and the pass transistor ( 101 ).

2 ) The current sense circuit of claim 1 , comprises an output transistor which is controlled by the output of the DD amplifier; wherein an output port of the output transistor is coupled to the output port of the sense transistor; and wherein a sense current through the output transistor provides an indication of a current through the pass transistor.

3 ) The current sense circuit of claim 2 , wherein the sense current through the output transistor is fed back to the control ports of the pass transistor and of the sense transistor.

4 ) The current sense circuit of claim 3 , further comprising a current source configured to set a control current; wherein a voltage level at the control ports of the pass transistor and of the sense transistor is dependent on the control current.

5 ) The current sense circuit of any of claim 3 , further comprising one or more current mirrors for mirroring the sense current to the control ports of the pass transistor and of the sense transistor.

6 ) The current sense circuit of claim 1 , wherein the differential amplifier comprises an offset compensated differential amplifier or an amplifier with a relatively low offset.

7 ) The current sense circuit of claim 6 , wherein the differential amplifier comprises
an analog-to-digital converter configured to derive a digital signal from the voltages at the differential input of the differential amplifier; a digital filter configured to filter the digital signal, to provide a filtered signal; and a digital-to-analog converter configured to derive voltages at the differential output of the differential amplifier based on the filtered signal.

8 ) The current sense circuit of claim 7 , wherein the differential amplifier further comprises a dithering unit configured to apply a dither signal to the voltages at the differential input of the differential amplifier.

9 ) The current sense circuit of claim 1 , wherein the differential amplifier comprises a first sub-amplifier and a second sub-amplifier that are arranged in parallel with regards to the differential input and the differential output of the differential amplifier.

10 ) The current sense circuit of claim 9 , wherein the first sub-amplifier and the second sub-amplifier are operated in an auto-zero phase and in an amplification phase in an alternating manner.

11 ) The current sense circuit of claim 10 , wherein the first sub-amplifier and the second sub-amplifier are operated in the auto-zero phase in a mutually exclusive manner, such that the first sub-amplifier is in the amplification phase, when the second sub-amplifier is in the auto-zero phase, and such that the second sub-amplifier is in the amplification phase, when the first sub-amplifier is in the auto-zero phase.

12 ) The current sense circuit of claim 10 , wherein
the differential amplifier comprises auto-zero capacitors for the first sub-amplifier; the auto-zero capacitors are arranged in series with an input port of the first sub-amplifier, when the first sub-amplifier is in the auto-zero phase; and the auto-zero capacitors couple the input port of the first sub-amplifier to ground, when the first sub-amplifier is in the amplification phase.

13 ) The current sense circuit of claim 10 , wherein the alternation of the auto-zero phase and of the amplification phase is controlled using a clock signal ( 300 , 301 , 302 ).

14 ) The current sense circuit of claim 1 , wherein
the pass transistor, the sense transistor and the output transistor are metal oxide semiconductor transistors; the input port of the pass transistor and of the sense transistor is a drain or a source; the output port of the pass transistor, of the sense transistor and of the output transistor is a source or a drain; and the control port of the pass transistor and of the sense transistor is a gate.

15 ) A method for providing a sense current which is indicative of a current through a pass transistor, the method comprising,
arranging a sense transistor such that an input port of the sense transistor is coupled to an input port of the pass transistor and such that a control port of the sense transistor is coupled to a control port of the pass transistor; amplifying a delta voltage corresponding to a difference between a pass voltage at an output port of the pass transistor and a sense voltage at an output port of the sense transistor to provide a second delta voltage; amplifying the delta voltage and the second delta voltage using respective differential input ports of a differential difference amplifier, referred to as DD amplifier, to provide a differential output voltage; using an output of the DD amplifier to control a voltage drop across the sense transistor and the pass transistor.

16 ) The method according to claim 15 , further comprising the step of:
providing an output transistor which is controlled by the output of the DD amplifier, wherein an output port of the output transistor is coupled to the output port of the sense transistor; and wherein a sense current through the output transistor provides an indication of a current through the pass transistor.

17 ) The method according to claim 16 , wherein the sense current through the output transistor is fed back to the control ports of the pass transistor and of the sense transistor.

18 ) The method according to claim 17 , further comprising the step of:
setting a control current by a current source; wherein a voltage level at the control ports of the pass transistor and of the sense transistor is dependent on the control current.

19 ) The method according to claim 17 , further comprising the step of:
mirroring by one or more current mirrors the sense current to the control ports of the pass transistor and of the sense transistor.

20 ) The method according to claim 15 , wherein the differential amplifier comprises an offset compensated differential amplifier or an amplifier with a relatively low offset.

21 ) The method according to claim 20 , wherein using the differential amplifier comprises the steps of:
deriving with an analog-to-digital converter a digital signal from the voltages at the differential input of the differential amplifier; filtering with a digital filter the digital signal

Assignees

• Dialog Semiconductor Uk Ltd

Inventors

• Gerna Danilo
• Scaldaferri Stefano
• Nizza Nicolo

Classifications

• G01R19/0092 Primary

  Measuring current only · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03F2203/45634

  the LC comprising one or more switched capacitors · CPC title

• H03F2203/45551

  the IC comprising one or more switched capacitors · CPC title

• H03K2217/0027

  Measuring means of, e.g. currents through or voltages across the switch · CPC title