Test board unit and apparatus for testing a semiconductor chip including the same

US2016262255A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016262255-A1
Application numberUS-201514846053-A
CountryUS
Kind codeA1
Filing dateSep 4, 2015
Priority dateMar 4, 2015
Publication dateSep 8, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A test board unit may include a test board, a thermal tank and a heat-dissipating plate. The test board may be configured to provide a semiconductor chip with a test current. The thermal tank may be configured to dissipate heat generated in the semiconductor chip. The heat-dissipating plate may be coupled between the test board and the thermal tank and may be configured to transfer the heat from the semiconductor chip to the thermal tank.

First claim

Opening claim text (preview).

What is claimed is: 1 . A test board unit comprising: a test board configured to provide a semiconductor chip with a test current; a thermal tank configured to dissipate heat generated from the semiconductor chip; and a heat-dissipating plate interposed between the test board and the thermal tank and configured to transfer the heat to the thermal tank. 2 . The test board unit of claim 1 , wherein the thermal tank is in direct contact with the heat-dissipating plate. 3 . The test board unit of claim 1 , further comprising an insulating layer formed on an outer surface of the thermal tank. 4 . The test board unit of claim 1 , wherein the thermal tank has at least one heat-dissipating hole. 5 . The test board unit of claim 1 , further comprising a heat-dissipating via arranged in the test board to electrically connect the semiconductor chip with the heat-dissipating plate. 6 . The test board unit of claim 5 , wherein the heat-dissipating via include a thermal via having a copper layer formed on an inner surface of the thermal via. 7 . The test board unit of claim 1 , wherein the test board comprises a test pattern configured to provide the semiconductor chip with the test current, and the heat-dissipating plate is electrically connected to the test pattern. 8 . A test board unit comprising: a test board configured to provide a semiconductor chip with a test current; a thermal tank configured to dissipate heat generated from the semiconductor chip; and a heat-dissipating via arranged in the test board to electrically couple the semiconductor chip with the thermal tank. 9 . The test board unit of claim 8 , wherein the thermal tank is in contact with the test board. 10 . The test board unit of claim 9 , wherein substantially no gap exists between the thermal tank and the test board. 11 . The test board unit of claim 8 , further comprising an insulating layer formed on an outer surface of the thermal tank. 12 . The test board unit of claim 8 , wherein the thermal tank has at least one heat-dissipating hole. 13 . The test board unit of claim 8 , wherein the test board comprises a test pattern configured to provide the semiconductor chip with the test current, and the heat-dissipating plate is electrically connected to the test pattern. 14 . An apparatus for testing a semiconductor chip, the apparatus comprising: a test board configured to provide the semiconductor chip with a test current; a socket arranged on the test board and configured to accept the semiconductor chip; a thermal tank configured to dissipate heat generated from the semiconductor chip; and a heat-dissipating plate coupled between the test board and the thermal tank and configured to transfer the heat to the thermal tank. 15 . The apparatus of claim 14 , wherein the socket is arranged on a first surface of the test board, and the heat-dissipating plate is arranged on a second surface of the test board opposite to the first surface. 16 . The apparatus of claim 14 , wherein the socket comprises electrode terminals electrically connected to the semiconductor chip, and the heat-dissipating plate is configured to surround the electrode terminals of the socket. 17 . The apparatus of claim 14 , further comprising a heat-dissipating via arranged in the test board to electrically connect the semiconductor chip with the heat-dissipating plate. 18 . An apparatus for testing a semiconductor chip, the apparatus comprising: a test board configured to provide the semiconductor chip with a test current; a socket arranged on the test board and configured to accept the semiconductor chip; a thermal tank configured to dissipate heat generated from the semiconductor chip; and a heat-dissipating via arranged in the test board and configured to electrically couple the semiconductor chip with the thermal tank. 19 . The apparatus of claim 18 , wherein the socket is arranged on a first surface of the test board, and the heat-dissipating plate is arranged on a second surface of the test board opposite to the first surface. 20 . The apparatus of claim 18 , wherein the thermal tank includes at least one heat-dissipating fin located on a lower surface of the thermal tank.

Assignees

Inventors

Classifications

  • H10P74/207Primary

    Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

  • H05K1/0206Primary

    by printed thermal vias · CPC title

  • Contacting devices, e.g. sockets, burn-in boards or mounting fixtures (in general G01R1/04) · CPC title

  • Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets (G01R1/067 takes precedence; mass production testing systems G01R31/59; testing of connections G01R31/66; for testing printed circuit boards G01R31/2808) · CPC title

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Frequently asked questions

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What does patent US2016262255A1 cover?
A test board unit may include a test board, a thermal tank and a heat-dissipating plate. The test board may be configured to provide a semiconductor chip with a test current. The thermal tank may be configured to dissipate heat generated in the semiconductor chip. The heat-dissipating plate may be coupled between the test board and the thermal tank and may be configured to transfer the heat fro…
Who is the assignee on this patent?
Sk Hynix Inc, Unitest Inc
What technology area does this patent fall under?
Primary CPC classification H10P74/207. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Sep 08 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).