Managing reuse information for memory pages

Patent metadata

Field	Value
Publication number	US-2016259732-A1
Application number	US-201514637579-A
Country	US
Kind code	A1
Filing date	Mar 4, 2015
Priority date	Mar 4, 2015
Publication date	Sep 8, 2016
Grant date	—

Abstract

Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor and at least one guest operating system. The managing includes: translating from virtual addresses to intermediate physical addresses using mappings in a first page table accessed by the guest operating system; translating from the intermediate physical addresses to physical addresses using mappings in a second page table accessed by the hypervisor; determining reuse information for a second memory page mapped by both the first page table and the second page table based on estimated reuse of data stored within the second memory page; storing the determined reuse information in both the first page table and the second page table; and using the stored reuse information to store cache lines in selected portions of a first cache.

First claim

What is claimed is:

1 . A method for managing address translation and caching, the method comprising:
retrieving a first memory page from a storage device in response to a page fault issued after an attempt to retrieve data in the first memory page from a physical address space of a main memory of an external memory system; issuing the attempt to retrieve the data in the first memory page in response to a cache miss issued after an attempt to retrieve the data in the first memory page from a first cache line of a first cache of the external memory system; and managing address translation and caching from a processor that includes (1) at least one memory management unit coupled to the external memory system, and (2) at least one central processing unit configured to run a hypervisor and at least one guest operating system, the managing including:
translating from virtual addresses in a virtual address space to intermediate physical addresses in an intermediate physical address space using mappings in a first page table accessed by the guest operating system;
translating from the intermediate physical addresses to physical addresses in the physical address space of the main memory using mappings in a second page table accessed by the hypervisor;
determining reuse information for a second memory page mapped by both the first page table and the second page table based on estimated reuse of data stored within the second memory page;
storing the determined reuse information in both the first page table and the second page table; and
using the stored reuse information to store cache lines in selected portions of the first cache.

2 . The method of claim 1 , wherein the estimated reuse of data stored within the second memory page comprises an estimated miss rate for blocks of data within the second memory page that are attempted to be retrieved from corresponding cache lines of the first cache.

3 . The method of claim 2 , wherein the estimated miss rate for blocks of data within the second memory page comprises an average miss rate of multiple blocks of data within the second memory page accessed during previous execution of the guest operating system.

4 . The method of claim 1 , wherein storing the determined reuse information in both the first page table and the second page table includes: (1) storing first reuse information determined by the guest operating system in the first page table, and (2) storing second reuse information determined by the hypervisor in the second page table.

5 . The method of claim 4 , wherein determining reuse information for the second memory page mapped by both the first page table and the second page table based on estimated reuse of data stored within the second memory page includes: (1) determining the first reuse information based on miss rates associated with virtual addresses, and (2) determining the second reuse information based on miss rates associated with intermediate physical addresses.

6 . The method of claim 4 , wherein using the stored reuse information to store cache lines in selected portions of the first cache includes processing the first reuse information and the second reuse information and using a result of the processing to store cache lines in selected portions of the first cache.

7 . The method of claim 6 , wherein the first reuse information is stored independently from: (1) any bits used to indicate virtual addresses, and (2) any bits used to indicate intermediate physical addresses.

8 . The method of claim 6 , wherein the second reuse information is stored independently from: (1) any bits used to indicate intermediate physical addresses, and (2) any bits used to indicate physical addresses.

9 . The method of claim 1 , wherein the managing further includes updating at least one of: (1) reuse information stored in an entry of the first page table, or (2) reuse information stored in an entry of the second page table.

10 . The method of claim 9 , wherein the updating is performed while preserving all bits of mapped addresses within the entry of the first or second page table.

11 . The method of claim 1 , wherein the first cache comprises a last level cache.

12 . An apparatus comprising:
a storage device configured to store memory pages including a first memory page retrieved from the storage device in response to a page fault issued after an attempt to retrieve data in the first memory page from a physical address space, where the attempt to retrieve the data in the first memory page from the physical address space is issued in response to a cache miss; an external memory system including: (1) a main memory controller coupled to main memory having the physical address space, and (2) a first cache configured to store a plurality of cache lines and to issue the cache miss after an attempt to retrieve the data in the first memory page from at least one of the cache lines; and a processor that includes (1) at least one memory management unit coupled to the external memory system, and (2) at least one central processing unit configured to run a hypervisor and at least one guest operating system; wherein the processor is configured to:
translate from virtual addresses in a virtual address space to intermediate physical addresses in an intermediate physical address space using mappings in a first page table accessed by the guest operating system;
translate from the intermediate physical addresses to physical addresses in the physical address space of the main memory using mappings in a second page table accessed by the hypervisor;
determine reuse information for a second memory page mapped by both the first page table and the second page table based on estimated reuse of data stored within the second memory page;
store the determined reuse information in both the first page table and the second page table; and
use the stored reuse information to store cache lines in selected portions of the first cache.

13 . The apparatus of claim 12 , wherein the estimated reuse of data stored within the second memory page comprises an estimated miss rate for blocks of data within the second memory page that are attempted to be retrieved from corresponding cache lines of the first cache.

14 . The apparatus of claim 13 , wherein the estimated miss rate for blocks of data within the second memory page comprises an average miss rate of multiple blocks of data within the second memory page accessed during previous execution of the guest operating system.

15 . The apparatus of claim 12 , wherein storing the determined reuse information in both the first page table and the second page table includes: (1) storing first reuse information determined by the guest operating system in the first page table, and (2) storing second reuse information determined by the hypervisor in the second page table.

16 . The apparatus of claim 15 , wherein determining reuse information for the second memory page mapped by both the first page table and the second page table based on estimated reuse of data stored within the second memory page includes: (1) determining the first reuse information based on miss rates associated with virtual addresses, and (2) determining the second reuse information based on miss rates associated with intermediate physical addresses.

17 . The apparatus of claim 15 , wherein using the stored reuse information to store cache lines in selected portions of the first cache includes processing the first reuse information and the second reuse information and using a result of the processing to store cache lines in se

Assignees

• Cavium Inc

Inventors

• Mukherjee Shubhendu Sekhar

Classifications

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F2212/283

  Plural cache memories · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F2212/68

  Details of translation look-aside buffer [TLB] · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title