Cache system with a primary cache and an overflow fifo cache

Patent metadata

Field	Value
Publication number	US-2016259728-A1
Application number	US-201414889114-A
Country	US
Kind code	A1
Filing date	Dec 12, 2014
Priority date	Oct 8, 2014
Publication date	Sep 8, 2016
Grant date	—

Abstract

A cache memory system including a primary cache and an overflow cache that are searched together using a search address. The overflow cache operates as an eviction array for the primary cache. The primary cache is addressed using bits of the search address, and the overflow cache is configured as a FIFO buffer. The cache memory system may be used to implement a translation lookaside buffer for a microprocessor.

First claim

What is claimed is:

1 . A cache memory system, comprising:
a primary cache memory including a first plurality of storage locations organized as a plurality of sets and a corresponding plurality of ways; an overflow cache memory that operates as an eviction array for said primary cache memory, wherein said overflow cache memory includes a second plurality of storage locations organized as a first-in, first-out buffer; and wherein said primary cache memory and said overflow cache memory are searched together for a stored value that corresponds with a received search address.

2 . The cache memory system of claim 1 , wherein said overflow cache array comprises N storage locations and N corresponding comparators, wherein each of said N storage locations stores a corresponding one of N stored addresses and a corresponding one of N stored values, and wherein each of said N comparators compares said search address with a corresponding one of said N stored addresses to determine a hit within said overflow cache array.

3 . The cache memory system of claim 2 , wherein said N stored addresses and said search address each comprise a virtual address, wherein each of said N stored values comprises a corresponding one of N physical addresses, and wherein said overflow cache array outputs a corresponding one of said N physical addresses that corresponds with said search address when said hit occurs.

4 . The cache memory system of claim 1 , wherein an entry stored within any one of said first plurality of storage locations that is evicted from said primary cache memory is pushed onto said first-in, first-out buffer of said overflow cache memory.

5 . The cache memory system of claim 1 , further comprising:
a level two cache; wherein said primary cache memory and said overflow cache memory collectively comprise a level one cache; and wherein an entry stored within one of said second plurality of storage locations that is evicted from said overflow cache memory is stored in said level two cache.

6 . The cache memory system of claim 1 , wherein said primary cache memory and said overflow cache memory each comprise a translation lookaside buffer for storing a plurality of physical addresses of a main system memory for a microprocessor.

7 . The cache memory system of claim 1 , wherein said primary cache memory comprises 16 sets by 4 ways of storage locations, and wherein said first-in, first-out buffer of said overflow cache memory comprises 8 storage locations.

8 . The cache memory system of claim 1 , further comprising:
logic that combines a first number of hit signals and a second number of hit signals into one hit signal; wherein said primary cache memory comprises said first number of ways and a corresponding first number of comparators providing said first number of hit signals; and wherein said overflow cache memory comprises said second number of comparators providing said second number of hit signals.

9 . The cache memory system of claim 1 , wherein:
said primary cache memory is operative to evict a tag value from one of said first plurality of storage locations within said primary cache memory and to form a victim address by appending said evicted tag value with an index value stored within said one of said first plurality of storage locations, and to evict a victim value from said one of said first plurality of storage locations that corresponds with said victim address; and wherein said victim address and said victim value collectively form a new entry that is pushed onto said first-in, first out buffer of said overflow cache array.

10 . The cache memory system of claim 1 , further comprising:
wherein a retrieved entry for storage into said primary cache memory includes an address comprising a tag value and a primary index, wherein said primary index is provided to an index input of said primary cache memory, and wherein said tag value is provided to a data input of said primary cache memory; wherein said primary cache memory is operative to select an entry corresponding to one of said plurality of ways of a set indicated by said primary index, to evict a tag value from said selected entry and to form a victim address by appending said evicted tag value with an index value of said selected entry, and to evict a victim value from said selected entry that corresponds with said victim address; and wherein said victim address and said victim value collectively form a new entry pushed onto said first-in, first out buffer of said overflow cache array.

11 . A microprocessor, comprising:
an address generator that provides a virtual address; and a cache memory system, comprising:
a primary cache memory including a first plurality of storage locations organized as a plurality of sets and a corresponding plurality of ways;
an overflow cache memory that operates as an eviction array for said primary cache memory, wherein said overflow cache memory includes a second plurality of storage locations organized as a first-in, first-out buffer; and
wherein said primary cache memory and said overflow cache memory are searched together for a stored physical address that corresponds with said virtual address.

12 . The microprocessor of claim 11 , wherein said overflow cache array comprises N storage locations and N corresponding comparators, wherein each of said N storage locations stores a corresponding one of N stored virtual addresses and a corresponding one of N physical addresses, and wherein each of said N comparators compares said virtual address from said address generator with a corresponding one of said N stored virtual addresses to determine a hit within said overflow cache array.

13 . The microprocessor of claim 11 , wherein an entry stored within any one of said first plurality of storage locations that is evicted from said primary cache memory is pushed onto said first-in, first-out buffer of said overflow cache memory.

14 . The microprocessor of claim 11 , wherein:
said cache memory system includes a level two cache; wherein said primary cache memory and said overflow cache memory collectively comprise a level one cache; and wherein an entry evicted from said overflow cache memory is stored in said level two cache.

15 . The microprocessor of claim 14 , further comprising:
a tablewalk engine that accesses system memory to retrieve said stored physical address when a miss occurs in said cache memory system; wherein said stored physical address found in either one of said level two cache and said system memory is stored in said primary cache memory; and wherein an entry evicted from said primary cache memory is pushed onto said first-in, first-out buffer of said overflow cache memory.

16 . The microprocessor of claim 11 , wherein said cache memory system further comprises:
logic that combines a first plurality of hit signals and a second plurality of hit signals into one hit signal for said cache memory system; wherein said primary cache memory comprises said first number of ways and a corresponding first number of comparators providing said first number of hit signals; and wherein said overflow cache memory comprises said second number of comparators providing said second number of hit signals.

17 . The microprocessor of claim 11 , wherein said cache memory system comprises a level one translation lookaside buffer for storing a plurality of physical addresses that correspond with a plurality of virtual addresses.

18 . The microprocessor of claim 17 , further comprising:
a tablewalk engine that accesses sy

Assignees

• Via Alliance Semiconductor Co Ltd

Inventors

• Eddy Colin
• Hooker Rodney E

Classifications

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F2212/602

  Details relating to cache prefetching · CPC title

• G06F2212/68

  Details of translation look-aside buffer [TLB] · CPC title

• G06F12/128

  adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel · CPC title

• G06F12/0871

  Allocation or management of cache space · CPC title