Memory system

Patent metadata

Field	Value
Publication number	US-2016259589-A1
Application number	US-201514852254-A
Country	US
Kind code	A1
Filing date	Sep 11, 2015
Priority date	Mar 6, 2015
Publication date	Sep 8, 2016
Grant date	—

Abstract

According to one embodiment, a memory system includes a nonvolatile memory, a buffer, a battery and a processing circuit. The battery stores energy supplied from the outside. The processing circuit, after start of the supply of energy from the outside, starts the acceptance of a request from the outside, starts a process in accordance with the accepted request, and restricts the amount of data in the buffer referring to a voltage of the battery. The process uses the buffer.

First claim

What is claimed is:

1 . A memory system comprising:
a nonvolatile memory; a buffer; a battery configured to store energy supplied from the outside; and a processing circuit configured to, after start of the supply of energy from the outside, start the acceptance of a request from the outside, start a process in accordance with the accepted request, the process using the buffer, and restrict the amount of data in the buffer referring to a voltage of the battery.

2 . The memory system according to claim 1 , wherein the processing circuit writes the data in the buffer into the memory using the energy stored in the battery after stop of the supply of energy from the outside.

3 . The memory system according to claim 2 , wherein the processing circuit computes a limit value based on the referred voltage and writes data in the buffer into the memory to prevent the amount of the data in the buffer from exceeding the computed limit value.

4 . The memory system according to claim 3 , wherein
the buffer includes a plurality of sub-buffers configured to be capable of shutting off the supply of energy individually, and the processing circuit shuts off the supply of energy to a sub-buffer in which the data is not stored, among the plurality of sub-buffers.

5 . The memory system according to claim 3 , wherein
the processing circuit
writes the data in the buffer in first mode into the memory after the start of the supply of energy from the outside and in a case where the battery being in a first state,
writes the data in the buffer in second mode into the memory after the start of the supply of energy from the outside and in a case where the battery being in a second state,
the first state is a state where the voltage of the battery is smaller than a set value, the second state is a state where the voltage of the battery is larger than the set value, and the second mode is a mode where the number of bits per memory cell is larger than the first mode.

6 . The memory system according to claim 5 , wherein the processing circuit writes the data in the buffer in the first mode into the memory after the stop of the supply of energy from the outside.

7 . The memory system according to claim 3 , wherein
the memory includes first and second memory chips, and the processing circuit
writes the data in the buffer in first mode into the memory after the start of the supply of energy from the outside and in a case where the battery being in a first state,
writes the data in the buffer in second mode into the memory after the start of the supply of energy from the outside and in a case where the battery being in a second state,
the first state is a state where the voltage of the battery is smaller than a set value, the second state is a state where the voltage of the battery is larger than the set value, the first mode is a mode where one of the first and second memory chips is operated and the other is not operated, and the second mode is a mode where both of the first and second memory chips are operated.

8 . The memory system according to claim 3 , wherein
the data is data requested from the outside to be written, and the processing circuit controls the acceptance of the data requested from the outside to be written and prevents the amount of the data in the buffer from exceeding the computed limit value.

9 . The memory system according to claim 3 , wherein
the processing circuit manages corresponding information between a logical address and a physical address, and generates changed information, the changed information being an updated part of the corresponding information or an added part of the corresponding information, and the data is the changed information.

10 . The memory system according to claim 9 , wherein the processing circuit controls the update of the corresponding information and prevents the amount of the changed information in the buffer from exceeding the computed limit value.

11 . A memory system comprising:
a nonvolatile memory; a battery configured to store energy supplied from the outside; a processing circuit configured to
write data in the buffer in first mode into the memory after start of the supply of energy from the outside and in a case where the battery being in a first state, the first state being a state where a voltage of the battery is smaller than a set value, and
write the data in the buffer in second mode into the memory after the start of the supply of energy from the outside and in a case where the battery being in a second state, the second mode being a mode where the number of bits per memory cell is larger than the first mode, the second state being a state where the voltage of the battery is larger than the set value.

12 . The memory system according to claim 11 , further comprising a buffer, wherein after the start of the supply of energy from the outside, the processing circuit
starts the acceptance of a request from the outside, starts a process in accordance with the accepted request, the process using the buffer, and writes the data in the buffer into the memory using the energy stored in the battery after stop of the supply of energy from the outside.

13 . The memory system according to claim 12 , wherein the processing circuit writes the data in the buffer in the first mode into the memory after the stop of the supply of energy from the outside.

14 . The memory system according to claim 12 , wherein the processing circuit refers to the voltage of the battery and restricts the amount of the data in the buffer.

15 . The memory system according to claim 14 , wherein the processing circuit
computes a limit value based on the referred voltage and writes the data in the buffer into the memory to prevent the amount of the data in the buffer from exceeding the computed limit value.

16 . The memory system according to claim 15 , wherein
the buffer includes a plurality of sub-buffers configured to be capable of shutting off the supply of energy individually, and the processing circuit shuts off the supply of energy to a sub-buffer in which the data is not stored, among the plurality of sub-buffers.

17 . The memory system according to claim 15 , wherein
the memory includes first and second memory chips, and the processing circuit
writes the data in the buffer in third mode into the memory after the start of the supply of energy from the outside and in a case where the battery being in a third state,
writes the data in the buffer in fourth mode into the memory after the start of the supply of energy from the outside and in a case where the battery being in a fourth state,
the third state is a state where the voltage of the battery is smaller than a set value, the fourth state is a state where the voltage of the battery is larger than the set value, the third mode is a mode where one of the first and second memory chips is operated and the other is not operated, and the fourth mode is a mode where both of the first and second memory chips are operated.

18 . The memory system according to claim 15 , wherein
the data is data requested from the outside to be written, and the processing circuit controls the acceptance of the data requested from the outside to be written and prevents the amount of data in the buffer from exceeding the computed limit value.

19 . The memory system according to claim 15 , wherein
the processing circuit manages corresponding information between a logical address and a physical address,

Assignees

• Toshiba Kk

Inventors

• Zettsu Tatsuya
• Kojima Yoshihisa
• Ueki Katsuhiko

Classifications

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F1/00

  Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00 (architectures of general purpose stored program computers G06F15/76) · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title