Interface to full and reduced pin jtag devices

Patent metadata

Field	Value
Publication number	US-2016259003-A1
Application number	US-201615159171-A
Country	US
Kind code	A1
Filing date	May 19, 2016
Priority date	Oct 18, 2006
Publication date	Sep 8, 2016
Grant date	—

Abstract

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices ( 504 ), only reduced pin JTAG devices ( 506 ), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface ( 502 ) between the substrate ( 408 ) and a JTAG controller ( 404 ). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

First claim

What is claimed is:

1 . A shadow protocol circuit comprising:
(a) a shadow protocol detection circuit having a test data in input, a test clock input, a test mode select input, an enable output, a command output, a command control output, a match input, an address output, and an address control output; (b) a command circuit having a command input connected to the command output, a command control input connected to the command control output, a full pin select output, and a reduced pin select output; and (c) an address circuit including:
i. a shift register having an address input coupled to the address output, an address clock input coupled to the address control output, and a shifted address output;
ii. an update register having an input coupled to the shifted address output, an address update input, and an update output;
iii. a device address circuit having a device address output; and
iv. comparator circuitry having an input coupled to the device address output, an input coupled to the update output, and a match output coupled to the match input.

2 . The shadow protocol circuit of claim 1 including a mode gate having one input connected to the test mode select input, and another input connected to the enable output.

3 . The shadow protocol circuit of claim 1 including a tri-state gate having one input connected to a test data out lead, an output connected to a gated test data out lead, and a control input connected to the enable output.

Assignees

• Texas Instruments Inc

Inventors

• Whetsel Lee D

Classifications

• G01R31/31703

  Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193) · CPC title

• G01R31/31725

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title

• G01R31/318558

  Addressing or selecting of subparts of the device under test · CPC title

• G01R31/31713 Primary

  Input or output interfaces for test, e.g. test pins, buffers (for scan test G01R31/318572) · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title