Pressure sensor having a bossed diaphragm

Patent metadata

Field	Value
Publication number	US-2016257561-A1
Application number	US-201615049314-A
Country	US
Kind code	A1
Filing date	Feb 22, 2016
Priority date	Jan 7, 2014
Publication date	Sep 8, 2016
Grant date	—

Abstract

A method includes forming a mask that defines a masked area and an unmasked area on a front side of a substrate, and implanting a buried layer corresponding to the unmasked area on the front side of the substrate. The method also includes forming an epitaxial layer having a back side on the front side of the substrate and on a front side of the buried layer, and creating an opening into a back side of the substrate up to a back side of the epitaxial layer and a back side of the one or portions of the buried layer.

First claim

What is claimed is:

1 . A method comprising:
forming a mask on a front side of a substrate, wherein the mask defines a masked area and an unmasked area; implanting a buried layer corresponding to the unmasked area on the front side of the substrate; forming an epitaxial layer on the front side of the substrate and on a front side of the buried layer, wherein the epitaxial layer has a back side; and creating an opening into a back side of the substrate up to a back side of the epitaxial layer and a back side of the one or portions of the buried layer.

2 . The method of claim 1 , further comprising:
heating the substrate. to diffuse the buried layer in the substrate, wherein edges and corners of the buried layer are rounded or smoothed in response to the heating.

3 . The method of claim 1 , wherein creating the opening forms a diaphragm consisting of a portion of the silicon epitaxial layer having a perimeter formed by one or more portions of the buried layer and a boss formed by a portion of the buried layer, wherein the boss is situated on the diaphragm.

4 . The method of claim 3 , wherein creating the opening further forms one or more legs on the epitaxial layer connecting the boss to the one or more portions of the buried layer at the perimeter of the diaphragm.

5 . The method of claim 4 , wherein the one or more legs have a minimum width near or at the perimeter of the diaphragm and a maximum width near or at the boss.

6 . The method of claim 5 , wherein a ratio of the maximum width to the minimum width is between about 1.1 to about 2.

7 . The method of claim 4 , further comprising:
forming one or more piezoresistive sensors on the front side of the epitaxial layer.

8 . The method of claim 7 , wherein the one or more piezoresistive sensor are formed over or near the one or more legs.

9 . The method of claim 8 , further comprising:
forming electronics in the epitaxial layer laterally adjacent to the diaphragm and connected to the one or more piezoresistive sensors.

10 . The method of claim 1 , wherein the substrate comprises a silicon substrate.

11 . The method of claim 1 , wherein the epitaxial layer comprises silicon.

12 . The method of claim 1 , wherein creating the opening comprises etching the back side of the substrate up to the back side of the epitaxial layer and the back side of the buried layer.

13 . A method for making a pressure sensor system comprising:
implanting a patterned buried layer, based on a masking, at a front side of a silicon substrate; heating the substrate to diffuse the buried layer in the substrate to round or smooth edges and corners of the buried layer; forming a silicon epitaxial layer having a back side on the front side of the silicon substrate and on a front side of the buried layer; and creating an opening, as defined by masking, into a back side of the substrate up to a back side of the epitaxial layer and a back side of the one or portions of the buried layer.

14 . The method of claim 13 , wherein the patterned buried layer reveals in the opening a diaphragm consisting of a portion of the silicon epitaxial layer having a perimeter formed by one or more portions of the buried layer on the epitaxial layer and having a boss formed by a portion of the buried layer, the boss being situated on the diaphragm.

15 . The method of claim 14 , wherein the patterned buried layer further reveals in the opening, one or more legs on the epitaxial layer connecting the boss to the one or more portions of the buried layer at the perimeter of the diaphragm.

16 . The method of claim 15 , wherein the one or more legs have a minimum width near or at the perimeter of the diaphragm and a maximum width near or at the boss.

17 . The method of claim 15 , further comprising:
forming one or more piezoresistive sensors on the diaphragm.

18 . The method of claim 17 , further comprising:
forming one or more piezoresistive sensors on the diaphragm, wherein the one or more sensors are situated near or on the one or more legs.

19 . The method of claim 17 , further comprising:
forming electronics in the epitaxial layer laterally adjacent to the diaphragm and connected to the one or more piezoresistive sensors.

20 . The method of claim 17 , further comprising:
obtaining and amplifying, by the electronics, signals from the one or more piezoresistive sensors indicating magnitudes of deflection of the diaphragm that represent pressures affecting the diaphragm.

Assignees

• Honeywell Int Inc

Inventors

• Stewart Carl
• Davis Richard
• Morales Gilberto

Classifications

• B81C1/00158 Primary

  Diaphragms, membranes (manufacture process for semi-permeable inorganic membranes B01D67/0039) · CPC title

• B81C2201/0198

  for making a masking layer · CPC title

• G01L9/0054

  integral with a semiconducting diaphragm · CPC title

• B81C2203/0728

  Pre-CMOS, i.e. forming the micromechanical structure before the CMOS circuit · CPC title

• G01L9/0055

  bonded on a diaphragm · CPC title