Precision batch production method for manufacturing ferrite rods

Patent metadata

Field	Value
Publication number	US-2016254579-A1
Application number	US-201415027286-A
Country	US
Kind code	A1
Filing date	Oct 1, 2014
Priority date	Oct 7, 2013
Publication date	Sep 1, 2016
Grant date	—

Abstract

The present invention relates to a method of manufacturing a ferrite rod. The method comprises etching cavities into two semiconductor substrates and depositing ferrite layers into the cavities. The semiconductor substrates are attached to each other such that the ferriote layers form a ferrite rod. The present invention employs conventional photolithography and bulk isotropic micromachining of semiconductor wafers to precisely and repeatably form a template or mould, into which magnetic material can be deposited to form a Faraday rotation or phase-shifting element.

First claim

1 . A method of manufacturing a ferrite rod, the method comprising the steps of:
etching a first cavity into a first surface of a first semiconductor substrate; depositing a first ferrite layer into the first cavity; etching a second cavity into a second surface of a second semiconductor substrate; depositing a second ferrite layer into the second cavity; attaching the first surface of the first semiconductor substrate to the second surface of the second semiconductor substrate such that the first ferrite layer contacts the second ferrite layer.

2 . The method of claim 1 , wherein said etching the first cavity into the first semiconductor substrate and said etching the second cavity into the second semiconductor substrate each comprise:
performing isotropic semiconductor etching to selectively remove a layer of the semiconductor substrate; and growing a passivation layer on the semiconductor substrate.

3 . The method of claim 1 , wherein etching the first cavity into the first semiconductor substrate and etching the second cavity into the second semiconductor substrate each comprise:
growing a first passivation layer on the semiconductor substrate; applying a resist coating to the first passivation layer; performing a lithography and developing step to selectively remove the resist coating; performing a first etching step to selectively remove the first passivation layer; stripping the resist coating from the first passivation layer; performing isotropic semiconductor etching to selectively remove a layer of the semiconductor substrate; stripping the first passivation layer; and growing a second passivation layer.

4 . The method of claim 3 , wherein said first etching step comprises an anisotropic etching step, and wherein said growing a first passivation layer comprises
thermally oxidising the semiconductor substrate such that the first passivation layer comprises a first oxidation layer; and/or applying low-stress low-pressure chemical vapour deposition to the semiconductor substrate such that the first passivation layer comprises a nitride layer.

5 . The method of claim 1 , wherein said depositing a ferrite layer into the cavity comprises:
arc plasma spraying of the ferrite layer in powder form; and/or performing wet chemical deposition of the ferrite layer.

6 . The method of claim 5 , wherein said depositing a ferrite layer into the cavity further comprises:
annealing of the ferrite layer; chemical mechanical polishing of the ferrite layer and/or hot phosphoric acid wet etching of the ferrite layer.

7 . The method of claim 2 , wherein attaching the first surface of the first semiconductor substrate to the second surface of the second semiconductor substrate comprises, for at least one semiconductor substrate of the first and second semiconductor substrates:
applying a resist coating to a surface of the semiconductor substrate comprising the first or second cavity; performing a lithography and developing step to selectively remove the resist coating; performing a first etching step to selectively remove at least a part of the passivation stripping the resist coating from the surface of the semiconductor substrate; assembling the first and second semiconductor substrates such that the respective first and second surfaces face each other.

8 . The method of claim 7 , wherein the method further comprises the steps of
chemical mechanical polishing of the first surface of the first semiconductor substrate;
applying a second resist coating;
performing a lithography and developing step to selectively remove the second resist coating; and
heating the assembled structure comprising the first and second semiconductor substrates.

9 . The method of claim 8 , wherein the method further comprises the steps of
depositing a gold and adhesion layer on the second surface of the second semiconductor substrate; etching the gold and adhesion layer; and stripping the second resist coating;
wherein said heating the assembled structure comprises heating the assembled structure to create eutectic Gold:Silicon bonds.

10 . The method of claim 8 , wherein the method further comprises the steps of
depositing a gold and adhesion layer on the second resist coating and on the second surface of the second semiconductor substrate; and lifting off the second resist coating;
wherein said heating the assembled structure comprises heating the assembled structure to create eutectic Gold:Silicon bonds.

11 . The method of claim 7 , wherein the method further comprises the steps of
applying a second resist coating; performing a lithography and developing step to selectively remove the second resist coating; and applying heat and pressure to the assembled structure comprising the first and second semiconductor substrates.

12 . The method of claim 11 , wherein the method further comprises the steps of
depositing a gold and adhesion layer on the respective first or second surface, wherein said applying a second resist coating comprises applying a second resist coating to the gold and adhesion layer; and etching the gold and adhesion layer; wherein the method further comprises the step of stripping of the second resist coating; wherein said applying heat and pressure to the assembled structure comprises applying heat and pressure to the assembled structure to create Gold:Gold bonds.

13 . The method of claim 7 , wherein the method further comprises applying a glue layer on the respective first or second surface; and
curing the glue layer.

14 . A ferrite rod comprising:
a first ferrite layer and a second ferrite layer;
wherein the ferrite rod further comprises a passivation layer arranged between said first ferrite layer and said second ferrite layer.

15 . An electronic device comprising:
a semiconductor substrate; and a ferrite rod;
wherein the ferrite rod is integrated in the semiconductor substrate.

16 . An electronic device as claimed in claim 15 .

17 . An electronic device as claimed in claim 15 , wherein the ferrite rod is integrated in the semiconductor substrate.

18 . An electronic device as claimed in claim 15 , wherein the electronic device comprises a phase shifting device that includes the ferrite rod.

Assignees

• Koninklijke Philips Nv

Inventors

• Mills John Brean

Classifications

• H10P14/69398

  the material having a perovskite structure, e.g. BaTiO3 · CPC title

• H01P1/19 Primary

  using a ferromagnetic device · CPC title

• H01P3/12

  Hollow waveguides (H01P3/20 takes precedence) · CPC title

• H01F41/14

  for applying magnetic films to substrates · CPC title

• H01P11/00

  Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type · CPC title