Array substrate and manufacturing method thereof
US-12185597-B2 · Dec 31, 2024 · US
US2016254335A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016254335-A1 |
| Application number | US-201615068095-A |
| Country | US |
| Kind code | A1 |
| Filing date | Mar 11, 2016 |
| Priority date | Dec 7, 2012 |
| Publication date | Sep 1, 2016 |
| Grant date | — |
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Disclosed are an organic light emitting diode device, and a method for fabricating the same. The organic light emitting diode device comprises a non-active area formed outside an active area of a substrate; a switching thin film transistor and a driving thin film transistor at each of the pixel regions; a planarization layer on the substrate; a first electrode on the planarization layer; a bank formed in the non-active area outside each pixel region; an organic light emitting layer on the first electrode; a second electrode on an entire surface of the substrate; a first passivation layer on the substrate; an organic layer on the first passivation layer; a second passivation layer on the organic layer and the first passivation layer; a barrier film disposed to face the substrate.
Opening claim text (preview).
1 - 6 . (canceled) 7 . A method for fabricating an organic light emitting diode device, the method comprising: providing a substrate divided into an active area including a plurality of pixel regions, and a non-active area formed outside the active area; forming a switching thin film transistor and a driving thin film transistor at each of the pixel regions on the substrate; forming a planarization layer on the substrate including the switching thin film transistor and the driving thin film transistor; forming a moisture blocking portion at the planarization layer in the non-active area; forming, on the planarization layer, a first electrode connected to a drain electrode of the driving thin film transistor; forming a bank in the non-active area outside each pixel region of the substrate including the first electrode; forming an organic light emitting layer on the first electrode in the pixel region; forming a second electrode on an entire surface of the substrate including the organic light emitting layer; forming a first passivation layer on an entire surface of the substrate including the second electrode; forming an organic layer on the first passivation layer; forming a second passivation layer on the organic layer and the first passivation layer; forming a barrier film so as to face the substrate; and forming an adhesive between the substrate and the barrier film, the adhesive configured to attach the substrate and the barrier film to each other to thus implement a panel state. 8 . The method of claim 7 , wherein the moisture blocking portion is formed in at least one in number, along an edge region of the non-active area of the substrate. 9 . The method of claim 7 , wherein the moisture blocking portion is formed at the planarization layer corresponding to driving circuit lines, in the non-active area of the substrate. 10 . The method of claim 9 , wherein the moisture blocking portion is formed at the planarization layer positioned above a driving circuit line to which a direct current is applied, among the gate driving circuit lines. 11 . The method of claim 7 , wherein an auxiliary electrode pattern, electrically connected to the first electrode and having a plurality of anode holes, is formed on the planarization layer, in the non-active area of the substrate. 12 . The method of claim 11 , wherein the auxiliary electrode pattern is simultaneously formed with the first electrode. 13 . The method of claim 7 , wherein the substrate is configured as one of a glass substrate, a flexible glass substrate and a plastic substrate.
comprising structures specially adapted for lowering the resistance · CPC title
multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers · CPC title
the pixel elements being TFTs · CPC title
Manufacture or treatment · CPC title
characterised by the compositions or shapes of the interlayer dielectrics · CPC title
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