Oxide semiconductor devices, methods of forming oxide semiconductor devices and organic light emitting display devices including oxide semiconductor devices

Patent metadata

Field	Value
Publication number	US-2016254334-A1
Application number	US-201514817900-A
Country	US
Kind code	A1
Filing date	Aug 4, 2015
Priority date	Feb 26, 2015
Publication date	Sep 1, 2016
Grant date	—

Abstract

An oxide semiconductor device includes a first insulation layer pattern and a second insulation layer pattern disposed on a substrate, an active layer disposed on the first and second insulation layer patterns, the active layer including a source region including the first insulation layer pattern, a drain region including the second insulation layer pattern, and a channel region disposed between the source and drain regions, a source electrode contacting the source region, and a drain electrode contacting the drain region.

First claim

What is claimed is:

1 . An oxide semiconductor device, comprising:
a substrate; a first insulation layer pattern and a second insulation layer pattern disposed on the substrate; an active layer disposed on the first insulation pattern and the second insulation layer pattern, the active layer comprising a source region comprising the first insulation layer pattern, a drain region comprising the second insulation layer pattern, and a channel region disposed between the source region and the drain region; a source electrode contacting the source region; and a drain electrode contacting the drain region.

2 . The oxide semiconductor device of claim 1 , wherein the source region and the drain region comprise impurities diffused from the first insulation layer pattern and the second insulation layer pattern, respectively.

3 . The oxide semiconductor device of claim 2 , wherein the impurities comprise hydrogen or nitrogen.

4 . The oxide semiconductor device of claim 3 , wherein each of the first and second insulation layer patterns comprises at least one of silicon oxyfluoride (SiO x F y ), silicon hydroxide (Si(OH) x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), and silicon fluoronitride (SiF y N x ).

5 . The oxide semiconductor device of claim 3 , wherein the active layer comprises at least one of indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), and magnesium (Mg).

6 . The oxide semiconductor device of claim 1 , wherein a length of the channel region varies according to impurity content of the source and drain regions.

7 . The oxide semiconductor device of claim 1 , further comprising a gate insulation layer disposed on the active layer, a gate electrode disposed on the gate insulation layer, and an insulating interlayer disposed on the gate insulation layer and the gate electrode.

8 . The oxide semiconductor device of claim 7 , wherein the source electrode and the drain electrode pass through the insulating interlayer and the gate insulation layer and contact the source region and the drain region, respectively.

9 . The oxide semiconductor device of claim 1 , further comprising:
a gate electrode disposed on the substrate; and a gate insulation layer disposed on the gate electrode and the substrate, wherein the first and second insulation layer patterns are disposed on the gate insulation layer.

10 . The oxide semiconductor device of claim 9 , wherein:
the source electrode contacts portions of the first insulation layer pattern and the source region; and the drain electrode contacts portions of the second insulation layer pattern and the drain region.

11 . The oxide semiconductor device of claim 9 , wherein the gate electrode does not overlap the source and drain electrodes.

12 . The oxide semiconductor device of claim 9 , further comprising an etch stop layer disposed on the active layer.

13 . A method for forming an oxide semiconductor device, the method comprising:
forming a first insulation layer pattern and second insulation layer pattern on a substrate; forming an active layer on the substrate, the first insulation layer pattern, and the second insulation layer pattern; forming a source region and a drain region in the active layer, the source region and the drain region comprising the first insulation layer pattern and the second insulation layer pattern, respectively; forming a gate insulation layer on the active layer; forming a gate electrode on the gate insulation layer; forming an insulating interlayer on the gate insulation layer and the gate electrode; and forming a source electrode and a drain electrode passing through the insulating interlayer and the gate insulation layer, the source electrode and the drain electrode contacting the source region and the drain region, respectively.

14 . The method of claim 13 , wherein forming the source and the drain electrodes comprise diffusing impurities from the first insulation layer pattern and the second insulation layer pattern into the active layer by a thermal treatment.

15 . The method of claim 14 , wherein the thermal treatment comprises an annealing process.

16 . The method of claim 13 , wherein forming the first insulation layer pattern and the second insulation layer pattern comprises:
forming an insulation layer on the substrate; forming a mask on the insulation layer; implanting impurities into portions of the insulation layer exposed by the mask; and patterning the insulation layer using the mask.

17 . The method of claim 13 , wherein forming the first insulation layer pattern and the second insulation layer pattern comprises:
forming an insulation layer comprising impurities on the substrate; forming a mask on the insulation layer; and patterning the insulation layer using the mask.

18 . An organic light emitting display device, comprising:
a substrate; an oxide semiconductor device disposed on the substrate, the oxide semiconductor device comprising a first insulation layer pattern, a second insulation layer pattern, an active layer comprising a source region comprising the first insulation layer pattern, a drain region comprising the second insulation layer pattern, and a channel region disposed between the source region and the drain region, a source electrode contacting the source region, and a drain electrode contacting the drain region; a first electrode electrically connected to the drain electrode; a light emitting layer disposed on the first electrode; and a second electrode disposed on the light emitting layer.

19 . The organic light emitting display device of claim 18 , wherein:
the oxide semiconductor device further comprises a gate insulation layer disposed on the active layer, a gate electrode disposed on the gate insulation layer, and an insulating interlayer disposed on the gate insulation layer and the gate electrode; and the source electrode and the drain electrode pass through the insulating interlayer and the gate insulation layer to contact the source region and the drain region, respectively.

20 . The organic light emitting display device of claim 18 , wherein:
the oxide semiconductor device further comprises a gate electrode disposed on the substrate and a gate insulation layer disposed on the gate electrode and the substrate; and the source electrode contacts portions of the first insulation layer pattern and the source region, and the drain electrode contacts portions of the second insulation layer pattern and the drain region.

Assignees

• Samsung Display Co Ltd

Inventors

• Yang Shin-Hyuk
• Kim Tae-Young
• Park Hye-Hyang

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/40

  into insulating materials · CPC title

• H10K59/123

  Connection of the pixel electrodes to the thin film transistors [TFT] · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title