Manufacturing method of array substrate, array substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-2016254292-A1
Application number	US-201514767759-A
Country	US
Kind code	A1
Filing date	Mar 20, 2015
Priority date	Oct 22, 2014
Publication date	Sep 1, 2016
Grant date	—

Abstract

The present invention provides a manufacturing method of an array substrate, an array substrate and a display apparatus. The manufacturing method comprises steps of: forming a thin film transistor and a signal line on a glass substrate, and forming an organic insulating layer above the thin film transistor and the signal line correspondingly; forming a passivation insulating layer on the organic insulating layer, wherein, before forming the passivation insulating layer, the manufacturing method further comprises a step of: performing a pre-heating process on the glass substrate on which the organic insulating layer is formed.

First claim

1 . A manufacturing method of an array substrate, comprising steps of: forming a thin film transistor and a signal line on a glass substrate, and forming an organic insulating layer above the thin film transistor and the signal line correspondingly; forming a passivation insulating layer on the organic insulating layer, wherein, before forming the passivation insulating layer, the manufacturing method further comprises a step of: performing a pre-heating process on the glass substrate on which the organic insulating layer is formed.

2 . The manufacturing method of claim 1 , wherein the passivation insulating layer includes a first passivation layer, and the signal line includes gate lines and data lines, wherein,
the step of forming the thin film transistor and the signal line on the glass substrate and forming the organic insulating layer above the thin film transistor and the signal line correspondingly comprises: step S 10 , forming the thin film transistor, the gate lines, the data lines and the organic insulating layer on the glass substrate, the organic insulating layer is formed above the thin film transistor, the gate lines and the data lines; the step of performing the pre-heating process on the glass substrate on which the organic insulating layer is formed comprises: step S 11 , performing the pre-heating process on the glass substrate subjected to the step S 10 ; and the step of forming the passivation insulating layer on the organic insulating layer comprises: step S 12 , forming the first passivation layer on the glass substrate subjected to the step S 11 .

3 . The manufacturing method of claim 2 , further comprises:
step S 13 , forming a first transparent electrode on the glass substrate subjected to the step S 12 .

4 . The manufacturing method of claim 3 , wherein the passivation insulating layer further includes a second passivation layer, the manufacturing method further comprises:
step S 14 , performing pre-heating process on the glass substrate subjected to the step S 13 ; step S 15 , forming the second passivation layer on the glass substrate subjected to the step S 14 .

5 . The manufacturing method of claim 4 , wherein the second passivation layer includes a buffer layer, a bottom passivation layer and a top passivation layer, and the step of forming the second passivation layer comprises:
step S 101 , depositing a buffer layer film for forming the buffer layer on the glass substrate subjected to the pre-heating process; step S 102 , depositing a bottom passivation layer film for forming the bottom passivation layer on the glass substrate subjected to the step S 101 ; step S 103 , depositing a top passivation layer film for forming the top passivation layer on the glass substrate subjected to the step S 102 ; and step 104 , forming a pattern of the second passivation layer by performing exposure, development and etching process once.

6 . The manufacturing method of claim 5 , wherein all of the buffer layer film, the bottom passivation layer film and the top passivation layer film are deposited by chemical vapor deposition method.

7 . The manufacturing method of claim 6 , wherein,
in the step S 101 , a deposition power for depositing the buffer layer film ranges from 6 kW to 20 kW, a deposition thickness ranges from 20 mm to 30 mm, a deposition pressure ranges from 600 mTorr to 1000 mTorr, a deposition gas is a mixed gas of SiH 4 , NH 3 and N 2 , gas flow ratio among SiH 4 , NH 3 and N 2 ranges from 1:2.3:15.6 to 1:16:45, and a deposition temperature ranges from 230° C. to 300° C.; in the step S 102 , the deposition power for depositing the bottom passivation layer film ranges from 6 kW to 18 kW, the deposition thickness ranges from 20 mm to 26 mm, the deposition pressure ranges from 1000 mTorr to 1500 mTorr, the deposition gas is a mixed gas of SiH 4 , NH 3 and N 2 , gas flow ratio among SiH 4 , NH 3 and N 2 ranges from 1:2.5:7.5 to 1:3.2:9.0, and the deposition temperature ranges from 230° C. to 300° C.; and in the step S 103 , the deposition power for depositing the top passivation layer film ranges from 6 kW to 15 kW, the deposition thickness ranges from 20 mm to 26 mm, the deposition pressure ranges from 1500 mTorr to 2000 mTorr, the deposition gas is a mixed gas of SiH 4 , NH 3 and N 2 , gas flow ratio among SiH 4 , NH 3 and N 2 ranges from 1:2.5:7.5 to 1:3.2:9.0, and the deposition temperature ranges from 230° C. to 300° C.

8 . The manufacturing method of claim 4 , further comprises:
step S 16 , forming a second transparent electrode on the glass substrate subjected to step S 15 .

9 . The manufacturing method of claim 8 , wherein the first transparent electrode is a pixel electrode and the second transparent electrode is a common electrode, or, the first transparent electrode is a common electrode and the second transparent electrode is a pixel electrode.

10 . The manufacturing method of claim 1 , wherein the passivation insulating layer includes a second passivation layer, and the signal line includes gate lines and data lines, wherein,
the step of forming the thin film transistor and the signal line on the glass substrate and forming the organic insulating layer above the thin film transistor and the signal line correspondingly comprises: step S 10 ′, forming the thin film transistor, the gate lines, the data lines, the organic insulating layer, a first passivation layer and a first transparent electrode on the glass substrate, the first passivation layer is formed above the thin film transistor, the gate lines and the data lines, the organic insulating layer is formed on the first passivation layer, the first transparent electrode is formed above the organic insulating layer; the step of performing pre-heating process on the glass substrate on which the organic insulating layer is formed comprises: step S 11 ′, performing pre-heating process on the glass substrate subjected to the step S 10 ′; and the step of forming the passivation insulating layer on the organic insulating layer comprises: step S 12 ′, forming the second passivation layer on the glass substrate subjected to the step S 11 ′.

11 . The manufacturing method of claim 10 , wherein the second passivation layer includes a buffer layer, a bottom passivation layer and a top passivation layer, and the step of forming the second passivation layer comprises:
step S 101 , depositing a buffer layer film for forming the buffer layer on the glass substrate subjected to the pre-heating process; step S 102 , depositing a bottom passivation layer film for forming the bottom passivation layer on the glass substrate subjected to the step S 101 ; step S 103 , depositing a top passivation layer film for forming the top passivation layer on the glass substrate subjected to the step S 102 ; and step S 104 , forming a pattern of the second passivation layer by performing exposure, development and etching process once.

12 . The manufacturing method of claim 11 , wherein all of the buffer layer film, the bottom passivation layer film and the top passivation layer film are deposited by chemical vapor deposition method.

13 . The manufacturing method of claim 12 , wherein,
in the step S 101 , a deposition power for depositing the buffer layer film ranges from 6 kW to 20 kW, a deposition thickness ranges from 20 mm to 30 mm, a deposition pressure ranges from 600 mTorr to 1000 mTorr, a deposition gas is a mixed gas of SiH 4 , NH 3 and N 2 , gas flow ratio among SiH 4 , NH 3 and N 2 ranges from 1:2.3:15.6 to 1:16:45, and a deposition temperature ranges from 230° C. to 300° C.; in the step S 102 , the deposition power for depositing the bottom passiva

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Shen Qiyu

Classifications

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6746

  Amorphous silicon · CPC title

• H10D30/6745

  Polycrystalline or microcrystalline silicon · CPC title

• H10D30/6732

  Bottom-gate only TFTs · CPC title