Methods of Making Integrated Circuit Assembly with Faraday Cage

Patent metadata

Field	Value
Publication number	US-2016254231-A1
Application number	US-201615154477-A
Country	US
Kind code	A1
Filing date	May 13, 2016
Priority date	Mar 27, 2013
Publication date	Sep 1, 2016
Grant date	—

Abstract

An integrated circuit assembly is formed with an insulating layer, a semiconductor layer, an active device, first, second, and third electrically conductive interconnect layers, and a plurality of electrically conductive vias. The insulating layer has a first surface and a second surface. The second surface is below the first surface. A substrate layer has been removed from the second surface. The semiconductor layer has a first surface and a second surface. The first surface of the semiconductor layer contacts the first surface of the insulating layer. The active device is formed in a region of the semiconductor layer. The first electrically conductive interconnect layer forms an electrically conductive ring. The second electrically conductive interconnect layer forms a first electrically conductive plate above the electrically conductive ring and the region of the semiconductor layer. The third electrically conductive interconnect layer forms a second electrically conductive plate below the electrically conductive ring and the region of the semiconductor layer. The plurality of electrically conductive vias electrically couple the electrically conductive ring to the first electrically conductive plate and to the second electrically conductive plate. The electrically conductive ring, the first electrically conductive plate, the second electrically conductive plate, and the plurality of electrically conductive vias form a Faraday cage around the active device.

First claim

What is claimed is:

1 . A method comprising:
forming an active device in a semiconductor layer of a wafer, the wafer further having an insulating layer and a substrate layer, the insulating layer being below the semiconductor layer, the substrate layer contacting the insulating layer and being below the insulating layer; forming a first electrically conductive interconnect layer with an electrically conductive ring; forming a second electrically conductive interconnect layer with a first electrically conductive plate above the electrically conductive ring and the active device; after forming the first and second electrically conductive interconnect layers, removing the substrate layer from the insulating layer; after removing the substrate layer, forming a third electrically conductive interconnect layer with a second electrically conductive plate below the electrically conductive ring, the insulating layer, and the active device; and forming a plurality of electrically conductive vias electrically coupling the electrically conductive ring to the first electrically conductive plate and to the second electrically conductive plate.

2 . The method of claim 1 , wherein the electrically conductive ring, the first electrically conductive plate, the second electrically conductive plate, and the plurality of electrically conductive vias form a Faraday cage around the active device.

3 . The method of claim 1 , further comprising:
forming the electrically conductive ring around a region above the active device.

4 . The method of claim 1 , further comprising:
forming a second active device in a region of the semiconductor layer outside of a boundary formed by the electrically conductive ring, the first electrically conductive plate, the second electrically conductive plate, and the plurality of electrically conductive vias; and forming an electrically conductive connection line disposed through an opening in the electrically conductive ring; wherein the electrically conductive connection line electrically connects the first active device to the second active device.

5 . The method of claim 1 , further comprising:
forming the first electrically conductive interconnect layer coupled to the semiconductor layer with the first electrically conductive ring around a region above the active device; forming a fourth electrically conductive interconnect layer coupled to the insulating layer with a second electrically conductive ring around a region below the active device; wherein the plurality of electrically conductive vias electrically couples the first electrically conductive ring to the second electrically conductive plate through the second electrically conductive ring.

6 . The method of claim 5 , further comprising:
forming a second active device in a region of the semiconductor layer outside of a boundary formed by the electrically conductive ring, the first electrically conductive plate, the second electrically conductive plate, and the plurality of electrically conductive vias; and forming an electrically conductive connection line disposed through an opening in the second electrically conductive ring; wherein the electrically conductive connection line electrically connects the first active device to the second active device.

7 . The method of claim 5 , further comprising:
forming a fifth electrically conductive interconnect layer with a third electrically conductive ring between the first electrically conductive ring and the first electrically conductive plate; wherein the plurality of electrically conductive vias electrically couples the first electrically conductive ring to the first electrically conductive plate through the third electrically conductive ring.

8 . The method of claim 7 , further comprising:
forming a sixth electrically conductive interconnect layer with a fourth electrically conductive ring between the second electrically conductive ring and the second electrically conductive plate; wherein the plurality of electrically conductive vias electrically couples the second electrically conductive ring to the second electrically conductive plate through the fourth electrically conductive ring.

9 . The method of claim 1 , further comprising:
forming the first electrically conductive plate and the second electrically conductive plate each with a plurality of holes.

10 . The method of claim 1 , further comprising:
bonding a handle wafer to a top side of the semiconductor wafer, wherein the handle wafer is disposed above the electrically conductive interconnect layers.

11 . A method comprising:
forming an active device in a first region of a semiconductor layer of a wafer, the wafer having an insulating layer, the semiconductor layer, and a substrate layer, the insulating layer having a first surface and a second surface, the second surface of the insulating layer being below the first surface of the insulating layer, the substrate layer contacting the second surface of the insulating layer, the semiconductor layer having a first surface and a second surface, the first surface of the semiconductor layer contacting the first surface of the insulating layer; forming a first electrically conductive interconnect layer with an electrically conductive ring; forming a second electrically conductive interconnect layer with a first electrically conductive plate above the electrically conductive ring and the first region of the semiconductor layer; removing the substrate layer from the second surface of the insulating layer; forming a third electrically conductive interconnect layer with a second electrically conductive plate below the electrically conductive ring, the insulating layer, and the first region of the semiconductor layer; and forming a plurality of electrically conductive vias electrically coupling the electrically conductive ring to the first electrically conductive plate and to the second electrically conductive plate; wherein the electrically conductive ring, the first electrically conductive plate, the second electrically conductive plate, and the plurality of electrically conductive vias form a Faraday cage around the active device.

12 . The method of claim 11 , further comprising:
forming the electrically conductive ring around a region above the first region of the semiconductor layer.

13 . The method of claim 11 , further comprising:
forming a second active device in a second region of the semiconductor layer outside the Faraday cage; forming an opening in the electrically conductive ring; and forming an electrically conductive connection line disposed through the opening in the electrically conductive ring; wherein the electrically conductive connection line electrically connects the first active device to the second active device.

14 . The method of claim 11 , further comprising:
forming the first electrically conductive interconnect layer coupled to the second surface of the semiconductor layer with the first electrically conductive ring around a region above the first region of the semiconductor layer; forming a fourth electrically conductive interconnect layer coupled to the second surface of the insulating layer with a second electrically conductive ring around a region below the first region of the semiconductor layer; wherein: the plurality of electrically conductive vias electrically couples the first electrically conductive ring to the second electrically conductive plate through the second electrically conductive ring; and the first electrically conductive ring, the first electrically conductive plate, the second electrically conduc

Assignees

• Qualcomm Inc

Inventors

• Stuber Michael A

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/218

  in silicon-on-insulator [SOI] wafers · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title