Reduction of Edge Effects from Aspect Ratio Trapping

Patent metadata

Field	Value
Publication number	US-2016254152-A1
Application number	US-201615151133-A
Country	US
Kind code	A1
Filing date	May 10, 2016
Priority date	Jul 1, 2008
Publication date	Sep 1, 2016
Grant date	—

Abstract

A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. Method and apparatus embodiments of the invention can reduce edge effects in semiconductor devices. Embodiments of the invention can provide a planar surface over a buffer layer between a plurality of uncoalesced ART structures.

First claim

What is claimed is:

1 . A structure comprising:
an insulating layer over a substrate, the insulating layer having a first opening to the substrate; a first crystalline semiconductor material in the first opening, the first crystalline semiconductor material being lattice mismatched to the substrate, the first crystalline semiconductor material having a lateral edge extending above a top surface of the insulating layer; a buffer semiconductor material over the top surface of the insulating layer, the buffer semiconductor material being a polycrystalline material; and a device formed in and/or above first crystalline material.

2 . The structure of claim 1 , wherein defects arising from the lattice mismatch within the first crystalline material terminate at a sidewall of the first opening.

3 . The structure of claim 1 , wherein the first crystalline material and the buffer semiconductor material are different materials.

4 . The structure of claim 1 further comprising:
a planar device layer over the first crystalline material and the buffer semiconductor material, the device being formed at least partially in the planar device layer.

5 . The structure of claim 1 , wherein the buffer semiconductor material is more defective than the first crystalline material.

6 . The structure of claim 1 , wherein a ratio of a height to a width of the first opening is equal to or greater than 0.5.

7 . The structure of claim 1 , wherein the substrate comprises a recess, the insulating layer overlying sidewalls of the recess.

8 . The structure of claim 1 , wherein the first crystalline material comprises a first region proximate the substrate and a second region over the first region, the second region having the lateral edge extending above a top surface of the insulating layer.

9 . The structure of claim 8 , wherein the second region of the first crystalline material is a different crystalline material than the first region of the first crystalline material.

10 . A structure comprising:
an insulating layer over a substrate, the insulating layer having a first opening to the substrate; a first crystalline semiconductor material in the first opening, the first crystalline semiconductor material being lattice mismatched to the substrate; a second crystalline semiconductor material over the first crystalline semiconductor material, the second crystalline semiconductor material having a lateral edge extending above a top surface of the insulating layer; a buffer semiconductor material over the top surface of the insulating layer, the buffer semiconductor material being an amorphous material; and a device formed in and/or above second crystalline material.

11 . The structure of claim 10 , wherein the first crystalline semiconductor material and the second crystalline semiconductor material are a same crystalline material.

12 . The structure of claim 10 , wherein the first crystalline semiconductor material and the second crystalline semiconductor material are different crystalline materials.

13 . The structure of claim 10 , wherein the first crystalline semiconductor material and the buffer semiconductor material are different materials.

14 . The structure of claim 10 further comprising:
a planar device layer over the second crystalline semiconductor material and the buffer semiconductor material, the device being formed at least partially in the planar device layer.

15 . The structure of claim 10 , wherein the buffer semiconductor material is more defective than the first crystalline semiconductor material.

16 . The structure of claim 10 , wherein the substrate comprises a recess, the insulating layer overlying sidewalls of the recess.

17 . A structure comprising:
an insulating layer over a substrate, the insulating layer having a first opening to the substrate; a first crystalline semiconductor material in the first opening, the first crystalline semiconductor material being lattice mismatched to the substrate, the first crystalline semiconductor material having a lateral edge extending above a top surface of the insulating layer; and a planar semiconductor layer over the insulating layer and the first crystalline semiconductor material, the planar semiconductor layer comprising a crystalline region over the first opening and an amorphous region adjacent the crystalline region.

18 . The structure of claim 17 further comprising:
a device formed above the planar semiconductor layer.

19 . The structure of claim 17 , wherein the substrate comprises a recess, the insulating layer overlying sidewalls of the recess.

20 . The structure of claim 17 , wherein the planar semiconductor layer is more defective than the first crystalline semiconductor material.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Zhiyuan

Classifications

• H10P14/2901

  Materials · CPC title

• H10P14/3411 Primary

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3256

  Microstructure · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P14/271

  characterised by the preparation of substrate for selective deposition · CPC title