Intelligent bandwidth shifting mechanism

Patent metadata

Field	Value
Publication number	US-2016253264-A1
Application number	US-201514595737-A
Country	US
Kind code	A1
Filing date	Jan 13, 2015
Priority date	Jan 13, 2015
Publication date	Sep 1, 2016
Grant date	—

Abstract

In an approach for sharing memory bandwidth in one or more processors, a processor receives a first set of monitored usage information for one or more processors executing one or more threads. A processor calculates impact of hardware data prefetching for each thread of the one or more threads, based on the first set of monitored usage information. A processor adjusts prefetch settings for the one or more threads, based on the calculated impact of hardware data prefetching for each thread of the one or more threads.

First claim

What is claimed is:

1 . A method for sharing memory bandwidth in one or more processors, the method comprising:
receiving a first set of monitored usage information for one or more processors executing one or more threads; calculating impact of hardware data prefetching for each thread of the one or more threads, based on the first set of monitored usage information; and adjusting prefetch settings for the one or more threads, based on calculated impact of hardware data prefetching for each thread of the one or more threads.

2 . The method of claim 1 , wherein the first set of monitored usage information comprises at least, for each thread of the one or more threads, instructions completed per cycle when prefetch is enabled, instructions completed per cycle when prefetch is disabled, memory bandwidth consumption when prefetch is enabled, and memory bandwidth consumption when prefetch is disabled; and
wherein the step of calculating the impact of hardware data prefetching for each thread of the one or more threads is based on at least instructions completed per cycle when prefetch is enabled, instructions completed per cycle when prefetch is disabled, memory bandwidth consumption when prefetch is enabled, and memory bandwidth consumption when prefetch is disabled.

3 . The method of claim 1 , wherein the first set of monitored usage information comprises at least, for each thread of the one or more threads, prefetch requests generated and prefetched data utilized; and
wherein the step of calculating the impact of hardware data prefetching for each thread of the one or more threads is based on at least prefetch requests generated and prefetched data utilized.

4 . The method of claim 1 , further comprising:
prior to receiving the first set of monitored usage information, adjusting the prefetch settings for the one or more threads to maximize prefetching for each thread of the one or more threads.

5 . The method of claim 1 , further comprising:
receiving a second set of monitored usage information for the one or more processors executing the one or more threads, subsequent to adjusting the prefetch settings for the one or more threads; determining that adjusted prefetch settings have a negative effect on the one or more processors executing the one or more threads, based on the second set of monitored usage information; and adjusting the prefetch settings for the one or more threads to a previous setting.

6 . The method of claim 1 , further comprising:
determining that memory bandwidth is saturated for the one or more processors executing the one or more threads, based on the first set of monitored usage information.

7 . The method of claim 1 , further comprising:
receiving a second set of monitored usage information for the one or more processors executing the one or more threads, subsequent to adjusting the prefetch settings for the one or more threads; and determining that the adjusted prefetch settings do not have a negative effect on the one or more processors executing the one or more threads, based on the second set of monitored usage information.

8 . A computer program product for sharing memory bandwidth in one or more processors, the computer program product comprising:
one or more computer readable storage media and program instructions stored on the one or more computer readable storage media, the program instructions comprising: program instructions to receive a first set of monitored usage information for one or more processors executing one or more threads; program instructions to calculate impact of hardware data prefetching for each thread of the one or more threads, based on the first set of monitored usage information; and program instructions to adjust prefetch settings for the one or more threads, based on calculated impact of hardware data prefetching for each thread of the one or more threads.

9 . The computer program product of claim 8 , wherein the first set of monitored usage information comprises at least, for each thread of the one or more threads, instructions completed per cycle when prefetch is enabled, instructions completed per cycle when prefetch is disabled, memory bandwidth consumption when prefetch is enabled, and memory bandwidth consumption when prefetch is disabled; and
wherein program instructions to calculate the impact of hardware data prefetching for each thread of the one or more threads are based on at least instructions completed per cycle when prefetch is enabled, instructions completed per cycle when prefetch is disabled, memory bandwidth consumption when prefetch is enabled, and memory bandwidth consumption when prefetch is disabled.

10 . The computer program product of claim 8 , wherein the first set of monitored usage information comprises at least, for each thread of the one or more threads, prefetch requests generated and prefetched data utilized; and
wherein program instructions to calculate the impact of hardware data prefetching for each thread of the one or more threads are based on at least prefetch requests generated and prefetched data utilized.

11 . The computer program product of claim 8 , further comprising:
program instructions, stored on the one or more computer readable storage media, to, prior to receiving the first set of monitored usage information, adjust the prefetch settings for the one or more threads to maximize prefetching for each thread of the one or more threads.

12 . The computer program product of claim 8 , further comprising:
program instructions, stored on the one or more computer readable storage media, to receive a second set of monitored usage information for the one or more processors executing the one or more threads, subsequent to adjusting the prefetch settings for the one or more threads; program instructions, stored on the one or more computer readable storage media, to determine that the adjusted prefetch settings have a negative effect on the one or more processors executing the one or more threads, based on the second set of monitored usage information; and program instructions, stored on the one or more computer readable storage media, to adjust the prefetch settings for the one or more threads to a previous setting.

13 . The computer program product of claim 8 , further comprising:
program instructions, stored on the one or more computer readable storage media, to determine that memory bandwidth is saturated for the one or more processors executing the one or more threads, based on the first set of monitored usage information.

14 . The computer program product of claim 8 , further comprising:
program instructions, stored on the one or more computer readable storage media, to receive a second set of monitored usage information for the one or more processors executing the one or more threads, subsequent to adjusting the prefetch settings for the one or more threads; and program instructions, stored on the one or more computer readable storage media, to determine that the adjusted prefetch settings do not have a negative effect on the one or more processors executing the one or more threads, based on the second set of monitored usage information.

15 . A computer system for sharing memory bandwidth in one or more processors, the computer system comprising:
one or more computer processors, one or more computer readable storage media, and program instructions stored on the computer readable storage media for execution by at least one of the one or more processors, the program instructions comprising: program instructions to receive a first set of monitored usage inform

Assignees

• IBM

Inventors

• Bose Pradip
• Buyuktosunoglu Alper
• Jimenez Perez Victor Javier
• O'Connell Francis P

Classifications

• G06F9/30047

  Prefetch instructions; cache control instructions · CPC title

• G06F9/3009

  Thread control instructions · CPC title

• G06F12/0862 Primary

  with prefetch · CPC title

• G06F2212/602

  Details relating to cache prefetching · CPC title

• G06F11/348

  Circuit details, i.e. tracer hardware · CPC title