Computer and memory control method

Patent metadata

Field	Value
Publication number	US-2016253263-A1
Application number	US-201414423613-A
Country	US
Kind code	A1
Filing date	Mar 4, 2014
Priority date	Mar 4, 2014
Publication date	Sep 1, 2016
Grant date	—

Abstract

A computer includes a first memory, a second memory having an I/O speed lower than an I/O speed of the first memory, a storage device, and a processor. The first memory has a work area and a first cache area where data input to and output from the storage device is temporarily stored and the second memory has a second cache area where the data input to and output from the storage device is temporarily stored and a swap area to be a saving destination of data stored in the work area. The processor reduces the work area and expands the first cache area, when an input/output amount to be an amount of data input to and output from the storage device is larger than a predetermined input/output amount.

First claim

1 . A computer comprising:
a first memory; a second memory that has an I/O speed lower than an I/O speed of the first memory; and a processor that is coupled to the first memory, the second memory, and a storage device, wherein the first memory has a work area and a first cache area where data input to and output from the storage device is temporarily stored, the second memory has a second cache area where the data input to and output from the storage device is temporarily stored and a swap area to be a saving destination of data stored in the work area, and when an input/output amount to be an amount of data input to and output from the storage device is larger than a predetermined input/output amount, the processor is configured to execute a first cache area expansion process for reducing the work area and expanding the first cache area.

2 . The computer according to claim 1 , wherein, when the occurrence frequency of saving data to the swap area is equal to or less than the predetermined occurrence frequency, the processor is configured to execute the first cache area expansion process.

3 . The computer according to claim 2 , wherein
when a write-back mode is set, the processor executes the first cache area expansion process, and when the write-hack mode is set and write data is written to the first cache area or the second cache area, the processor is configured to determine that write is completed and then writes the write data from the first cache area or the second cache area to the storage device.

4 . The computer according to claim 2 , wherein
when a write-through mode is set and a cache read error amount is larger than a difference between the input/output amount and the predetermined input/output amount, the processor is configured to execute the first cache area expansion process, when the write-through mode is set and write data is written to the storage device, the processor is configured to determine that write is completed, and the cache read error amount is a total amount of read data not hit to both data stored in the first cache area and data stored in the second cache area.

5 . The computer according to claim 2 , wherein
when a ratio of a use amount for a total amount of the work area and the swap area is larger than a first ratio, the processor is configured to expand the swap area and reduce the second cache area, when the ratio of the use amount is smaller than a second ratio, the processor is configured to reduce the swap area and expand the second cache area, and the second ratio is smaller than the first ratio.

6 . The computer according to claim 1 , wherein
a plurality of virtual machines are configured to be executed by the processor, the work area includes a virtual memory allocation area allocated to a virtual memory of each of the plurality of virtual machines, the second memory further has a swap area for a virtual machine allocated to each of the plurality of virtual machines, the first cache area expansion process is a process for reducing a virtual memory allocation area allocated to a virtual machine of a reduction target among the plurality of virtual machines, reducing the work area in the first memory, and expanding the first cache area, and the virtual machine of the reduction target is a virtual machine in which the swap occurrence frequency for the swap area for the virtual machine is equal to or less than the predetermined swap occurrence frequency.

7 . The computer according to claim 6 , wherein the processor is configured to
set a virtual machine in which a ratio of a use amount for a total amount of the virtual memory and the swap area for the virtual machine is larger than a third ratio, among the plurality of virtual machines, as a swap expansion candidate, set a virtual machine in which the ratio of the use amount smaller than a fourth ratio as a swap reduction candidate, and change a size of the second cache area in the second memory, on the basis of a difference of the swap area for the virtual machine allocated to each virtual machine corresponding to the swap expansion candidate and the swap area for the virtual machine allocated to each virtual machine corresponding to the swap reduction candidate.

8 . A memory control method comprising:
determining whether an input/output amount to be an amount of data to be input to and output from a storage device using at least one of a first cache area and a second cache area is larger than a predetermined input/output amount or not, the first cache area existing in a first memory, the second cache area existing in a second memory having an I/O speed lower than an I/O speed of the first memory, the first memory further having a work area, and, the second, memory further having a swap area to be a saving destination of data stored in the work area; and executing a first cache area expansion process for reducing the work area and expanding the first cache area, when the input/output amount is larger than the predetermined input/output amount.

Assignees

• Hitachi Ltd

Inventors

• Takada Aritoki

Classifications

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/0893

  Caches characterised by their organisation or structure · CPC title

• G06F2212/601

  Reconfiguration of cache memory · CPC title

• G06F12/0871 Primary

  Allocation or management of cache space · CPC title

• G06F2212/1048

  Scalability · CPC title