Testing front end modules, testing methods and modular testing systems for testing electronic equipment

Patent metadata

Field	Value
Publication number	US-2016253252-A1
Application number	US-201514633966-A
Country	US
Kind code	A1
Filing date	Feb 27, 2015
Priority date	Feb 27, 2015
Publication date	Sep 1, 2016
Grant date	—

Abstract

A testing front end module for testing a plurality of devices under test (DUT) includes a testing signal interface, a vector signal generator (VSG) coupled to the testing signal interface and configured to generate testing signals upon reception of testing routine signals from a remote controller via the testing signal interface, a vector signal analyser (VSA) coupled to the testing signal interface and configured to receive testing response signals from a plurality of DUTs and to transmit the received testing response signals to the remote controller via the testing signal interface, a multiplexer/demultiplexer (MUX/DEMUX) coupled to the VSG and the VSA, the MUX/DEMUX being configured to multiplex the received testing response signals and to demultiplex the generated testing signals, and a test device interface coupled to the MUX/DEMUX and configured to couple the testing front end module to the plurality of DUTs.

First claim

What is claimed is:

1 . A testing method for testing a plurality of devices under test (DUT), the method comprising:
transmitting testing routine signals from a remote controller to a testing front end module via a wired data connection between the remote controller and the testing front end module; generating testing signals in the testing front end module on the basis of the testing routine signals; and splitting the generated testing signals and transmitting the split testing signals from the testing front end module to a plurality of DUTs.

2 . The testing method of claim 1 , wherein the wired data connection is a USB connection, a PCIe connection, a Thunderbolt connection or a Firewire connection.

3 . The testing method of claim 2 , wherein the data rate of the wired data connection is at least 1 Mbps.

4 . The testing method of claim 2 , wherein the physical length of the cable of the wired data connection is at least 60 inches.

5 . A testing method for testing a plurality of devices under test (DUT), the method comprising:
generating testing signals in a testing front end module; splitting the generated testing signals and transmitting the split testing signals from the testing front end module to a plurality of DUTs; receiving testing response signals upon the split testing signals from each of the plurality of DUTs by the testing front end module; transmitting the received testing response signals from the testing front end module to a remote controller via a wired data connection between the remote controller and the testing front end module; and evaluating the testing response signals in the remote controller.

6 . The testing method of claim 5 , wherein the wired data connection is a USB connection, a PCIe connection, a Thunderbolt connection or a Firewire connection.

7 . The testing method of claim 6 , wherein the data rate of the wired data connection is at least 1 Mbps.

8 . The testing method of claim 6 , wherein the physical length of the cable of the wired data connection is at least 60 inches.

9 . A testing front end module for testing a plurality of devices under test (DUT), the testing front end module comprising:
a testing signal interface; a vector signal generator (VSG) coupled to the testing signal interface and configured to generate testing signals upon reception of testing routine signals from a remote controller via the testing signal interface; a vector signal analyser (VSA) coupled to the testing signal interface and configured to receive testing response signals from a plurality of DUTs and to transmit the received testing response signals to the remote controller via the testing signal interface; a multiplexer/demultiplexer (MUX/DEMUX) coupled to the VSG and the VSA, the MUX/DEMUX being configured to multiplex the received testing response signals and to demultiplex the generated testing signals; and a test device interface coupled to the MUX/DEMUX and configured to couple the testing front end module to the plurality of DUTs.

10 . The testing front end module of claim 9 , wherein the test device interface comprises at least four input/output ports configured to be connected to DUTs.

11 . The testing front end module of claim 10 , wherein the test device interface comprises at least eight input/output ports configured to be connected to DUTs.

12 . The testing front end module of claim 9 , wherein the testing signal interface comprises one or more of a USB port, a PCIe port, a Thunderbolt port and a Firewire port.

13 . The testing front end module of claim 9 , wherein the testing signal interface is configured to operate with a data rate of at least 1 Mbps.

14 . The testing front end module of claim 9 , further comprising:
a power supply interface coupled to the VSG and the VSA and configured to supply power to the VSG and the VSA from an external power supply coupled to the power supply interface.

15 . The testing front end module of claim 10 , wherein the MUX/DEMUX comprises at least one of a set of independently controllable attenuators, a set of independently controllable calibration units, and a switch fabric configured to selective switch the input/output ports of the test device interface to one of the VSA and the VSG.

16 . A testing system for testing a plurality of devices under test (DUT), the testing system comprising:
a controller; and a testing front end module, the testing front end module comprising:
a testing signal interface;
a vector signal generator (VSG) coupled to the testing signal interface and configured to generate testing signals upon reception of testing routine signals from the controller via the testing signal interface;
a vector signal analyser (VSA) coupled to the testing signal interface and configured to receive testing response signals from a plurality of DUTs and to transmit the received testing response signals to the controller via the testing signal interface;
a multiplexer/demultiplexer (MUX/DEMUX) coupled to the VSG and the VSA, the MUX/DEMUX being configured to multiplex the received testing response signals and to demultiplex the generated testing signals; and
a test device interface coupled to the MUX/DEMUX and configured to couple the testing front end module to the plurality of DUTs,
wherein the controller is coupled to the testing signal interface of the testing front end module via a wired data connection.

17 . The testing system of claim 16 , wherein the wired data connection comprises at least one cable and wherein the physical length of the cable of the wired data connection is at least 60 inches.

18 . The testing system of claim 16 , wherein the testing signal interface of the testing front end module comprises one or more of a USB port, a PCIe port, a Thunderbolt port and a Firewire port.

19 . The testing system of claim 16 , wherein the MUX/DEMUX of the testing front end module comprises at least one of a set of independently controllable attenuators, a set of independently controllable calibration units, and a switch fabric configured to selective switch input/output ports of the test device interface to one of the VSA and the VSG.

20 . The testing system of claim 16 , wherein the controller is configured to generate testing routine signals to be sent to the testing front end module via the testing signal interface, and wherein the controller is configured to evaluate the testing response signals from the plurality of DUTs sent from the testing front end module via the testing signal interface.

Assignees

• Rohde & Schwarz

Inventors

• Holzmann Gottfried
• Plaumann Ralf
• Wolanin Peter
• Dilling Wilfried
• Schindlmeier Rudolf
• Lorenzen Rolf
• Steinegger Anton
• Mittermaier Werner

Classifications

• G06F11/26

  Functional testing · CPC title

• G06F11/2294 Primary

  by remote test · CPC title

• G06F11/273

  Tester hardware, i.e. output processing circuits {(G06F11/263 takes precedence)} · CPC title

• H04B17/0085 Primary

  using test signal generators · CPC title