Semiconductor device

Patent metadata

Field	Value
Publication number	US-2016247820-A1
Application number	US-201615147656-A
Country	US
Kind code	A1
Filing date	May 5, 2016
Priority date	Dec 25, 2009
Publication date	Aug 25, 2016
Grant date	—

Abstract

A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a plurality of cell arrays arranged sequentially in a first direction, each of the plurality of cell arrays including a plurality of gates extending in the first direction and arranged in a second direction orthogonal to the first direction, wherein each of the plurality of cell arrays includes a first conductive type well region extending in the second direction and formed below the plurality of gates, wherein a first cell array of the plurality of cell arrays includes:
a first well potential supply region in the first conductive type well region, the first well potential supply region including impurities of same conductive type as the first conductive type well region,
first, second and third adjacent gates of the plurality of gates, wherein a portion of the first well potential supply region is disposed between the first adjacent gate and the second adjacent gate, and the third adjacent gate is disposed adjacent to the first adjacent gate,
the first, second and third adjacent gates are disposed at the same pitch in the second direction,
wherein a second cell array of the plurality of cell arrays adjacent to the first cell array in the first direction includes three gates of the plurality of gates, each of the three gates is opposed to at least one of the first, second and third adjacent gates of the first cell array in the first direction, and wherein the first, second, and third adjacent gates of the first cell array are dummy gates, and the first adjacent gate overlaps a portion of the first well potential supply region.

2 . The semiconductor device of claim 1 ,
wherein the second adjacent gate of the first cell array overlaps a portion of the first well potential supply region.

3 . The semiconductor device of claim 1 ,
wherein the first cell array further includes a second well potential supply region including impurities of an opposite conductive type of the first conductive type well region, wherein a portion of the second well potential supply region is disposed between the first and second adjacent gates, and wherein the first adjacent gate overlaps a portion of the second well potential supply region.

4 . The semiconductor device of claim 3 ,
wherein the second adjacent gate of the first cell array overlaps a portion of the second well potential supply region.

5 . A semiconductor device comprising:
a plurality of cell arrays arranged sequentially in a first direction, each of the plurality of cell arrays including a plurality of gates extending in the first direction and arranged in a second direction orthogonal to the first direction, wherein each of the plurality of cell arrays includes a first conductive type well region extending in the second direction and formed below the plurality of gates, wherein a first cell array of the plurality of cell arrays includes:
a first well potential supply region in the first conductive type well region, the first well potential supply region including impurities of same conductive type as the first conductive type well region; and
first, second and third adjacent gates of the plurality of gates, wherein the first adjacent gate is disposed on a first side of the first well potential supply region in the second direction, the second adjacent gate is disposed along a second side of the first well potential supply region opposite to the first side in the second direction, and the third adjacent gate is disposed adjacent to the first adjacent gate,
wherein the first, second, and third adjacent gates are disposed at the same pitch in the second direction,
wherein a second cell array of the plurality of cell arrays adjacent to the first cell array in the first direction includes three gates of the plurality of gates, each of the three gates is opposed to a respective one of the first, second and third adjacent gates of the first cell array in the first direction, and wherein the first, second, and third adjacent gates of the first cell array are dummy gates, and are disposed over a plane defined by two outer sides of the first well potential supply region.

6 . The semiconductor device of claim 5 ,
wherein the second adjacent gate is further disposed over a plane defined by four outer sides of the first well potential supply region.

7 . The semiconductor device of claim 5 ,
wherein the first cell array further includes a second well potential supply region including impurities of an opposite conductive type of the first conductive type well region, a first portion of the second well potential supply region is disposed between the first and second adjacent gates, and the first, second and third adjacent gates are disposed over a plane defined by two outer sides of the second well potential supply region.

Assignees

• Socionext Inc

Inventors

• Tamaru Masaki
• Nakanishi Kazuyuki
• Nishimura Hidetoshi

Classifications

• H10D84/991

  Latch-up prevention · CPC title

• H10D84/981

  Power supply lines · CPC title

• H10D84/966

  Gate electrode terminals or contacts · CPC title

• H10D84/0191

  Manufacturing their doped wells · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title