Led die dispersal in displays and light panels with preserving neighboring relationship

Patent metadata

Field	Value
Publication number	US-2016247704-A1
Application number	US-201615143748-A
Country	US
Kind code	A1
Filing date	May 2, 2016
Priority date	Oct 30, 2012
Publication date	Aug 25, 2016
Grant date	—

Abstract

A method of dispersing semiconductor chips from a wafer of semiconductor chips onto a substrate while preserving the neighboring relationship of each chip to each adjacent chip is disclosed. The method includes dispersing the wafer into sequential columns of semiconductor chips with a first pitch between columns while preserving the neighboring relationship and sequentially dispersing the columns of semiconductor chips into rows of individual chips with a second pitch between rows onto a substrate while preserving the neighboring relationship.

First claim

Having fully described the invention in such clear and concise terms as to enable those skilled in the art to understand and practice the same, the invention claimed is:

1 - 17 . (canceled)

18 . Apparatus designed to disperse semiconductor chips from a wafer of semiconductor chips onto a substrate while preserving the neighboring relationship of each chip to each adjacent chip, the apparatus comprising:
a movably mounted first carrier with a layer of releasable adhesive deposited thereon and having a wafer cut into individual chips in m columns and n rows releasably adhered thereon; a movably mounted intermediate carrier with a layer of releasable adhesive deposited thereon; a first element mounted for movement in synchronism with the movably mounted first carrier and the movably mounted intermediate carrier; first release apparatus positioned to release each sequential column from the first carrier; the first element being designed and positioned so that movement of the first element provides pressure between released sequential columns of the wafer and the first carrier to disperse the sequential columns of semiconductor chips to the intermediate carrier with a first pitch between columns while preserving the neighboring relationship, each released column being adhered to the intermediate carrier with the layer of releasable adhesive as each column is dispersed from the first carrier to the intermediate carrier; a second element mounted for movement in synchronism with the movably mounted intermediate carrier and a movably mounted substrate; second release apparatus positioned to release each sequential row from the intermediate carrier; and the second element being designed and positioned so that movement of the second element provides pressure between the intermediate carrier and released sequential rows of the wafer to disperse the sequential rows of semiconductor chips to a substrate with a second pitch between rows while preserving the neighboring relationship.

19 . Apparatus as claimed in claim 18 wherein the first element includes one of a rotating roller with pressure pads on the outer periphery and a reciprocating column.

20 . Apparatus as claimed in claim 18 wherein the second element includes one of a rotating roller with pressure pads on the outer periphery and a reciprocating column.

21 . Apparatus as claimed in claim 18 wherein the layer of releasable adhesive on the first carrier includes one of a UV releasable adhesive, a UV-releasable tape, a thermal transfer layer, or a laser induced sublimation transfer layer.

22 . Apparatus as claimed in claim 21 wherein the first release apparatus includes a UV radiation device.

23 . Apparatus as claimed in claim 18 wherein the layer of releasable adhesive on the intermediate carrier includes a UV releasable adhesive layer, a thermal transfer layer, or a laser induced sublimation transfer layer.

24 . Apparatus as claimed in claim 23 wherein the second release apparatus includes a UV radiation device.

25 . Apparatus as claimed in claim 18 wherein the semiconductor die chips dispersed are light emitting elements of one of a flat panel light source, a backlight unit in an active matrix LCD display, a passive matrix light emitting diode array, and a full-color active matrix display.

26 . Apparatus as claimed in claim 18 wherein the semiconductor die chips dispersed are of a sensing function and are being used as sensing elements in one of a light detector array, radiation detector array, a biosensor sensor array, or other type of sensor arrays.

27 . Apparatus as claimed in claim 18 wherein the wafer includes m columns and n rows of LED semiconductor chips each chip with a d 1 ×d 2 area, the first pitch being L 2 , and the second pitch being L 1 .

28 . Apparatus as claimed in claim wherein the substrate includes contact pads thereon, each contact pad having an area larger than the area of each LED semiconductor chip, and the contact pads positioned in m columns and n rows with the first pitch L 2 and the second pitch L 1 therebetween, and the sequentially dispersed columns of semiconductor chips from the intermediate carrier being dispersed into rows of individual chips on the rows of contact pads.

29 . Apparatus as claimed in claim wherein the m columns and n rows of the LED semiconductor chips each chip with a d 1 ×d 2 area provides a dilution factor in a range of 9 to 9000.

30 . A method of making electronic devices of large in x/z and y/z dimension ratio including the steps of:
Providing LED die chips each including at least two contact electrodes, one of the at least two contact electrodes being positioned on a lower surface of the LED die chip and one of the at least two contact electrodes being positioned on an upper surface of the LED die chip; dispersing the LED die chips from a wafer carrier into an array on a carrier substrate, with the array having a pre-defined dimension dilution factor and preserved neighboring relationship; forming an insulation planarization layer on the array among the dispersed LED die chips; and forming a passivation/optic layer on the array on top of the dispersed LED die chips.

31 . The method of claim 30 wherein the insulating planarization layer is formed by a solution coating process including one of slot coating, bar-coating, screen printing, or transfer printing.

32 . The method of claim 30 wherein the carrier substrate is flexible or conformable.

33 . The method of claim 30 wherein the top optical coating includes one of color filters, energy conversion filters, or micro-lenses.

34 . The method of claim 30 wherein the electronic device is one of a flat panel light source, a backlight unit in an active matrix LCD display, a passive matrix light emitting diode array, and a full-color active matrix display.

35 . The method of claim 30 wherein the electronic device is one of a solar cell panel, a light detector array, a radiation detector array, a biosensor sensor array, or other type of sensor arrays.

36 . The method of claim 30 including a step of connecting contact electrodes positioned on a lower surface of the LED die chips into a circuit on the substrate carrier.

37 . The method of claim 30 including a step of connecting contact electrodes positioned on an upper surface of the LED die chips to adjacent die chips and forming connections among the die chips and contact electrodes.

38 . The method of claim 30 wherein the carrier substrate comprises at least one contact pad for each contact electrode on the lower surface of each LED die chip and connecting electrically among different die chips or to peripheral areas outside the array area.

39 . The method of claim 30 wherein the carrier substrate comprises at least one contact pad for each contact electrode on the lower surface of each LED die chip and connecting electrically to a thin film transistor pixel driving circuit adjacent the LED die chip.

40 . The method of claim 39 wherein thin film transistors in the thin film transistor pixel driving circuit comprise metal-oxide active layers or poly-silicon active layers.

41 . The method of claim 39 wherein the thin film transistor pixel driving circuit adjacent each LED die chip comprises connections to at least one row electrode line and at least one column electrode line and connecting the pixel circuits and the LED die chips into an active array.

Assignees

• Shieh Chan-Long
• Yu Gang

Inventors

• Shieh Chan-Long
• Yu Gang

Classifications

• H10P72/7622

  characterised by supporting substrates others than wafers, e.g. chips · CPC title

• H10P72/7616

  characterised by a coating, a hardness or a material · CPC title

• H10P72/3212

  the substrates to be conveyed not being semiconductor wafers or large planar substrates, e.g. chips or lead frames · CPC title

• H10P72/0446 Primary

  Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title