Pulse width modulation (pwm) driving scheme and bezel reduction

Patent metadata

Field	Value
Publication number	US-2016247456-A1
Application number	US-201614988594-A
Country	US
Kind code	A1
Filing date	Jan 5, 2016
Priority date	Feb 20, 2015
Publication date	Aug 25, 2016
Grant date	—

Abstract

This application sets forth a circuit configuration for a light emitting diode (LED) or organic light emitting diode (OLED) display. The circuit configuration allows for the pulse-width modulation (PWM) of each emission signal sent to each line of the display. The PWM of each emission signal is accomplished using a gate-in-panel (GIP) controller of the display. The GIP controller uses an arrangement of shift register outputs and a programmable clock input to control an output of an inverter that provides the emission signal. The programmable clock input can be programmed according to a desired timing or duty cycle for the emission signal. In this way, by limiting the duty cycle of the emission signal, dimming and other display features can be exhibited by the LED or OLED display.

First claim

What is claimed is:

1 . A computer-implemented method for using a programmable clock input to a gate-in-panel (GIP) controller to perform pulse-width modulation (PWM) of an output signal provided to a line of a display by an inverter of the GIP controller, the method comprising:
by the inverter of the GIP controller: receiving a scanning signal from at least one shift register of the GIP controller; receiving a programmed output from the at least one shift register, wherein the programmed output is based on the programmable clock input to the GIP controller; and causing a pulse-width of the output signal to be adjusted according to a high or low state of each of the scanning signal and the programmed output.

2 . The computer-implemented method of claim 1 , wherein the scanning signal is a phase-shifted scanning signal provided by the at least one shift register.

3 . The computer-implemented method of claim 1 , wherein the programmable clock input is provided to the GIP controller from an integrated circuit (IC) driver of the display.

4 . The computer-implemented method of claim 1 , wherein the at least one shift register is configured to receive an output corresponding to an adjacent GIP controller connected to an adjacent line in the display.

5 . The computer-implemented method of claim 1 , wherein the programmable clock input provides for dimming control of the line of the display.

6 . The computer-implemented method of claim 1 , wherein an amount by which the line of the display is dimmed depends on timing of the programmable clock input

7 . The computer-implemented method of claim 1 , wherein the inverter receives multiple phase-shifted scanning signals provided by the at least one shift register.

8 . The computer-implemented method of claim 1 , wherein the at least one shift register operates according a two-phase clock input, a three-phase clock input, or a four-phase clock input.

9 . A system, comprising:
a gate-in-panel (GIP) controller; an integrated circuit (IC) driver configured to provide a programmable clock input to the GIP controller; and at least one display line connected to the GIP controller, wherein the GIP controller comprises:
i) at least one shift register configured to provide at least one scanning signal to the at least one display line; and
ii) an inverter connected to the at least one shift register, wherein the inverter is configured to output a pulse-width modulated (PWM) emission signal based on the programmable clock input provided to the at least one shift register and the at least one scanning signal.

10 . The system of claim 9 , wherein the programmable clock input provides for dimming control of the at least one display line.

11 . The system of claim 10 , wherein an amount by which the at least one display line is dimmed depends on timing of the programmable clock input.

12 . The system of claim 9 , wherein the at least one shift register is configured to receive an output corresponding to an adjacent GIP controller connected to an adjacent line in a display relative to the at least one display line.

13 . The system of claim 9 , wherein the at least one scanning signal is a phase-shifted scanning signal provided by the at least one shift register.

14 . The system of claim 9 , wherein the inverter receives multiple phase-shifted scanning signals provided by the at least one shift register.

15 . The system of claim 9 , wherein the at least one shift register operates according a two-phase clock input, a three-phase clock input, or a four-phase clock input.

16 . A gate-in-panel (GIP) controller, comprising:
a shift register configured to provide multiple scanning signals and a programmable clock output based on at least one clock input from an integrated circuit (IC) driver, and an inverter connected to a scanning signal of the multiple scanning signals and the programmable clock output of the shift register, wherein the inverter is configured to provide a pulse-width modulated (PWM) emission signal to a line of a display based on a timing of the programmable clock output and the scanning signal.

17 . The GIP controller of claim 16 , wherein the multiple scanning signals are phase-shifted scanning signals.

18 . The GIP controller of claim 16 , wherein the shift register is configured to operate according a two-phase clock input.

19 . The GIP controller of claim 16 , wherein the shift register is configured to operate according a three-phase clock input or a four-phase clock input.

20 . The GIP controller of claim 16 , wherein the programmable clock output provides for dimming control of the line of the display.

Assignees

• Apple Inc

Inventors

• Lin Hung Sheng
• Lin Chin-Wei
• Tsai Tsung-Ting
• Youn Sang Y
• Nho Hyunwoo

Classifications

• G09G3/2092

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title

• G09G3/2022

  using sub-frames · CPC title

• G11C19/00

  Digital stores in which the information is moved stepwise, e.g. shift registers · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title