Baseboard management systems and methods with distributed intelligence for multi-node platforms

Patent metadata

Field	Value
Publication number	US-2016246754-A1
Application number	US-201514625676-A
Country	US
Kind code	A1
Filing date	Feb 19, 2015
Priority date	Feb 19, 2015
Publication date	Aug 25, 2016
Grant date	—

Abstract

Baseboard management systems and methods with distributed intelligence for multi-node platforms. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include a plurality of modules, each of the plurality of modules including a plurality of nodes, each of the plurality of nodes including a system-on-chip (SoC), each of the plurality of SoCs including an integrated management controller (iMC), each of the plurality of iMCs configured to implement a first intelligent platform management interface (IPMI) stack having a first architecture; and a plurality of baseboard management controllers (BMCs), each of the BMCs disposed on a corresponding one of the plurality of modules, each of the BMCs coupled to the plurality of iMCs on the corresponding one of the plurality of modules, each of the plurality of iMCs configured to implement a second IPMI stack having a second architecture different from the first architecture.

First claim

1 . An Information Handling System (IHS), comprising:
a plurality of modules, each of the plurality of modules including a plurality of nodes, each of the plurality of nodes including a system-on-chip (SoC), each of the plurality of SoCs including an integrated management controller (iMC), each of the plurality of iMCs configured to implement a first intelligent platform management interface (IPMI) stack having a first architecture; and a plurality of baseboard management controllers (BMCs), each of the BMCs disposed on a corresponding one of the plurality of modules, each of the BMCs coupled to the plurality of iMCs on the corresponding one of the plurality of modules, each of the plurality of iMCs configured to implement a second IPMI stack having a second architecture different from the first architecture.

2 . The IHS of claim 1 , wherein the plurality of modules includes trays, blades, or sleds, and wherein the IHS further comprises a chassis configured to receive the trays, blades, or sleds.

3 . The IHS of claim 1 , wherein each of the plurality of SoCs include a processor and a memory coupled to the processor.

4 . The IHS of claim 1 , wherein the first architecture has a smaller number of components than the second architecture.

5 . The IHS of claim 1 , wherein the first architecture includes a sensor driver, a sensor monitor coupled to the sensor driver, and a first encapsulator coupled to the sensor driver, the first encapsulator configured to communicate sensor information to or from a corresponding BMC.

6 . The IHS of claim 5 , wherein the first encapsulator includes a Platform Level Data Model (PLDM)-to-management transport protocol mapper, a management transport protocol interface coupled to the PLDM-to-management transport protocol mapper, and an interconnect bus link coupled to the management transport protocol interface; and wherein the interconnect bus link is configured to communicate with the corresponding BMC.

7 . The IHS of claim 5 , wherein the first architecture further includes a host interface driver, a host interface message relay coupled to the host interface driver, and a second encapsulator coupled to the host interface message relay, the second encapsulator configured to communicate host interface information to or from the corresponding BMC.

8 . The IHS of claim 7 , wherein the first architecture further includes a universal asynchronous receiver/transmitter (UART) driver, a serial relay coupled to the UART driver, and a third encapsulator coupled to the serial relay, the third encapsulator configured to communicate UART information to or from the corresponding BMC.

9 . The IHS of claim 8 , wherein the corresponding BMC includes a first decapsulator configured to configured to communicate sensor information to or from the iMC, a second decapsulator configured to configured to communicate host interface information to or from the iMC, and a third decapsulator configured to configured to communicate UART information to or from the iMC.

10 . The IHS of claim 9 , wherein the first, second, and third decapsutators are each coupled to respective interfaces in the corresponding BMC, the corresponding BMC further configured to provide full IPMI processing.

11 . In an Information Handling System (IHS) having a plurality of trays, blades, or sleds, each given tray, blade, or sled having a single baseboard management controller (BMC) coupled to two or more of a plurality of nodes, each of the plurality of nodes including a processor, a memory, and an integrated management controller (iMC), each of the iMCs coupled to the single BMC, a method comprising:
implementing, via each of the plurality of iMCs, a first intelligent platform management interface (IPMI) stack having a first architecture, the first IPMI architecture configured to communicate sensor information, host interface messages, and serial instructions to the single BMC; and processing the sensor information, host interface messages, and serial instructions by the single BMC, wherein the single BMC is configured to implement a second IPMI stack having a second architecture, and wherein the second architecture is logically more complex than the first architecture.

12 . The method of claim 11 , wherein the first architecture includes a sensor driver, a sensor monitor coupled to the sensor driver, and a first encapsulator coupled to the sensor driver.

13 . The method of claim 12 , wherein the first encapsulator includes a Platform Level Data Model (PLDM)-to-management transport protocol mapper, a management transport protocol interface coupled to the PLDM-to-management transport protocol mapper, and an interconnect bus link coupled to the management transport protocol interface.

14 . The method of claim 12 , wherein the first architecture further includes a host interface driver, a host interface message relay coupled to the host interface driver, and a second encapsulator coupled to the host interface message relay.

15 . The method of claim 14 , wherein the first architecture further includes a universal asynchronous receiver/transmitter (UART) driver, a serial relay coupled to the UART driver, and a third encapsulator coupled to the serial relay.

16 . The method of claim 11 , wherein the second architecture includes a first decapsulator configured to configured to communicate sensor information to or from each iMC, a second decapsulator configured to configured to communicate host interface information to or from each iMC, and a third decapsulator configured to configured to communicate UART information to or from each iMC.

17 . In an Information Handling System (IHS) having a plurality of trays, blades, or sleds, each given tray, blade, or sled having a baseboard management controller (BMC) coupled to two or more of a plurality of nodes, each of the plurality of nodes including a processor, a memory, and an integrated management controller (iMC), a memory device having program instructions stored thereon that, upon execution, cause the IHS to:
implement, via each of the plurality of iMCs, a first intelligent platform management interface (IPMI) stack having a first architecture, the first IPMI architecture configured to communicate sensor information, host interface messages, and serial instructions to the BMC; and implement, via the BMC, IPMI processing of the sensor information, host interface messages, and serial instructions, wherein the BMC has a second IPMI stack having a second architecture different from the first architecture.

18 . The memory device of claim 17 , wherein each of the iMCs has a smaller footprint that the BMC.

19 . The memory device of claim 17 , wherein the first architecture includes:
a sensor driver, a sensor monitor coupled to the sensor driver, and a first encapsulator coupled to the sensor driver, the first encapsulator configured to communicate sensor information to or from the BMC; a host interface driver, a host interface message relay coupled to the host interface driver, and a second encapsulator coupled to the host interface message relay, the second encapsulator configured to communicate host interface information to or from the BMC; and a universal asynchronous receiver/transmitter (UART) driver, a serial relay coupled to the UART driver, and a third encapsulator coupled to the serial relay, the third encapsulator configured to communicate UART information to or from the BMC.

20 . The memory device of claim 19 , wherein the first encapsulator includes a Platform Level Data Model (PLDM

Assignees

• Dell Products Lp

Inventors

• Rao Balaji Bapu Gururaja
• Jreij Elie Antoun
• Lambert Timothy M
• Stuewe John R
• Suryanarayana Shekar Babu
• Vancil Paul W

Classifications

• G06F15/161

  Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning (casings, cabinets, racks or drawers for data centers H05K5/00) · CPC title

• G06F13/4286 Primary

  using a handshaking protocol, e.g. RS232C link · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F15/7807

  System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package · CPC title