Autonomously controlling a buffer of a processor

Patent metadata

Field	Value
Publication number	US-2016246352-A1
Application number	US-201315025575-A
Country	US
Kind code	A1
Filing date	Nov 27, 2013
Priority date	Nov 27, 2013
Publication date	Aug 25, 2016
Grant date	—

Abstract

In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.

First claim

What is claimed is:

1 . An apparatus comprising:
an input/output (I/O) buffer to couple a logic unit of the apparatus to a device coupled to the apparatus via a pad; and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state of the apparatus.

2 . The apparatus of claim 1 , further comprising a configuration storage coupled to the I/O buffer, the logic to program at least one field of the configuration storage based at least in part on the detected value.

3 . The apparatus of claim 2 , wherein the at least one field comprises a first field to store a control value for a first switch coupled between a supply voltage node and an output node of the I/O buffer, wherein when closed the first switch is to enable a pullup impedance to couple to the output node.

4 . The apparatus of claim 3 , wherein the at least one field comprises a second field to store a second control value for a second switch coupled between a reference voltage node and the output node of the I/O buffer, wherein when closed the second switch is to enable a pulldown impedance to couple to the output node.

5 . The apparatus of claim 4 , wherein the at least one field comprises a third field to store an enable signal to enable a transmitter of the I/O buffer.

6 . The apparatus of claim 1 , wherein the logic is to control the I/O buffer to provide an override value to the pad when an override indicator is active, wherein a software driver is to provide the override value.

7 . The apparatus of claim 1 , wherein the architectural state comprises an entry into a low power state.

8 . The apparatus of claim 1 , wherein the I/O buffer comprises:
a transmitter to receive a signal and to output the signal to the pad; a pullup resistance configured to be controllably coupled between a supply voltage node and an output node of the transmitter; and a pulldown resistance configured to be controllably coupled between a reference voltage node and the output node of the transmitter.

9 . The apparatus of claim 8 , wherein the I/O buffer further comprises a receiver to receive a second signal from the pad and to output the signal to the logic unit.

10 . A system comprising:
a processor formed in an integrated circuit (IC), the processor including:
at least one core;
an input/output (I/O) controller having a power management logic; and
at least one input/output (I/O) buffer coupled to the I/O controller to communicate signal information with one or more devices coupled to the processor, wherein the power management logic is to receive an indication of entry into a low power state of at least a portion of the processor, sample a value on a pad of the IC, the pad coupled between the at least one I/O buffer and an interconnect, determine a state of the value, and dynamically control the at least one I/O buffer, responsive to the state of the value; and
a dynamic random access memory (DRAM) coupled to the processor.

11 . The system of claim 10 , wherein the power management logic is to set a field of a control storage responsive to the sampled value, to cause coupling of at least one of a first impedance and a second impedance to an output node of the at least one I/O buffer.

12 . The system of claim 11 , wherein the power management logic is to sample the value, determine the state, and cause the coupling in a first mode, and in a second mode to cause the coupling based on an override value provided by a firmware or a software driver.

13 . The system of claim 12 , wherein the power management logic is to cause coupling of the first impedance or the second impedance to enable the I/O buffer to output a signal corresponding to the sampled value.

14 . A method comprising:
sampling a state on a pad of an integrated circuit (IC) coupled to an interconnect, the pad coupled to a buffer of the IC, the buffer including a transmitter and a receiver; selecting a control value for at least one controllable element of the buffer based on the sampled state; and determining whether an override indicator is active, and if so storing an override value in a storage associated with the buffer, and otherwise storing the control value in the storage.

15 . The method of claim 14 , further comprising controlling the buffer to maintain the sampled state using the stored control value.

16 . The method of claim 14 , further comprising receiving the override indicator from a firmware of the system.

17 . The method of claim 14 , further comprising controlling the buffer to place the pad into a tri-state before sampling the state.

18 . The method of claim 14 , wherein the storage comprises a plurality of fields including:
a first field to store a control value for a first switch coupled between a supply voltage node and an output node of the buffer; a second field to store a second control value for a second switch coupled between a reference voltage node and the output node of the buffer; a third field to store a third control value for a transmitter of the buffer; and a fourth field to store a fourth control value for a receiver of the buffer.

19 . The method of claim 14 , further comprising storing the sampled state in a second storage, and thereafter referencing the sampled state.

20 . The method of claim 14 , further comprising controlling the buffer to couple a pulldown impedance to the pad when the pad is unused in a platform including the IC.

21 . An apparatus comprising means to perform a method as claimed in any one of claims 14 to 20 .

22 . A machine-readable storage medium including machine-readable instructions, when executed, to implement a method as claimed in any one of claims 14 to 20 .

Assignees

• Intel Corp

Inventors

• Elias Vinu K
• Ramani Sundar
• Tomar Arvind S
• Liu Jianjun

Classifications

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title

• G11C2207/105

  Aspects related to pads, pins or terminals · CPC title

• H03K19/018592

  with a bidirectional operation · CPC title

• G06F1/3212 Primary

  Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title