Supperlattice buffer structure for gallium nitride transistors

Patent metadata

Field	Value
Publication number	US-2016240679-A1
Application number	US-201514620399-A
Country	US
Kind code	A1
Filing date	Feb 12, 2015
Priority date	Feb 12, 2015
Publication date	Aug 18, 2016
Grant date	—

Abstract

A transistor with a multi-strained layer superlattice (SLS) structure is provided. A first strained layer superlattice (SLS) layer is arranged over a substrate. A first buffer layer is arranged over the first SLS layer and includes dopants configured to increase a resistance of the first buffer layer. A second SLS layer is arranged over the first buffer layer. A second buffer layer is arranged over the second SLS layer and includes dopants configured to increase a resistance of the second buffer layer. A channel layer is arranged over the second buffer layer. An active layer is arranged over and directly abuts the channel layer. The channel and active layers collectively define a heterojunction. A method for manufacturing the transistor is also provided.

First claim

What is claimed is:

1 . A transistor comprising:
a first strained layer superlattice (SLS) layer arranged over a substrate; a first buffer layer arranged over the first SLS layer and including dopants configured to increase a resistance of the first buffer layer; a second SLS layer arranged over the first buffer layer; a second buffer layer arranged over the second SLS layer and including dopants configured to increase a resistance of the second buffer layer; a channel layer arranged over the second buffer layer; and an active layer arranged over and directly abutting the channel layer, wherein the channel and active layers collectively define a heterojunction.

2 . The transistor according to claim 1 , wherein the first SLS layer includes about 20 to about 100 pairs of lattice mismatched layers, and wherein a pair of lattice mismatched layers includes layers with mismatched lattice constants.

3 . The transistor according to claim 1 , wherein the second SLS layer includes about 20 to about 100 pairs of lattice mismatched layers, and wherein a pair of lattice mismatched layers includes layers with mismatched lattice constants.

4 . The transistor according to claim 1 , wherein the first SLS layer and the first buffer layer alternatingly repeat about 2 to about 20 times stacked between the substrate and the second buffer layer.

5 . The transistor according to claim 1 , further including:
a dielectric layer arranged over the active layer; a source electrode and a drain electrode arranged over the dielectric layer and extending to the active layer through the dielectric layer; and a gate electrode arranged over the dielectric layer and between the source electrode and the drain electrode.

6 . The transistor according to claim 5 , wherein the gate electrode extends into the dielectric layer, while remaining spaced from the active layer by the dielectric layer, and wherein the dielectric layer extends into the active layer.

7 . The transistor according to claim 5 , wherein the active layer is one of:
a single layer of aluminum gallium nitride (AlGaN); and a multilayer stack comprising an aluminum nitride (AlN) layer and an AlGaN layer overlying the AlN layer.

8 . The transistor according to claim 1 , further including:
a bottom active layer arranged over the channel layer; a top active layer arranged over a gate region of the channel layer; a pair of source/drain electrodes arranged over the bottom active layer and extending into the bottom active layer to the channel layer; and a gate electrode arranged over the top active layer and spaced from the bottom active layer by the top active layer.

9 . The transistor according to claim 8 , wherein the bottom active layer is a multilayer stack comprising an aluminum nitride (AlN) layer and an aluminum gallium nitride (AlGaN) layer arranged over the AlN layer, and wherein the top active layer is one of:
a p-type gallium nitride (GaN) layer; and a multilayer stack comprising a p-type GaN layer and an n-type GaN layer arranged over the p-type GaN layer.

10 . The transistor according to claim 1 , wherein the first or second SLS layer includes a plurality of pairs of lattice mismatched layers configured to collectively produce a compressive force, wherein a pair of lattice mismatched layers includes layers with mismatched lattice constants.

11 . The transistor according to claim 10 , wherein a pairs of lattice mismatched layers includes an aluminum nitride (AlN) layer and a gallium nitride (GaN) layer arranged over the AlN layer.

12 . A method for manufacturing a transistor, said method comprising:
forming a first strained layer superlattice (SLS) layer over a substrate; forming a first buffer layer over the first SLS layer, wherein the first buffer layer has a high resistance relative to the first SLS layer; forming a second SLS layer over the first buffer layer; forming a second buffer layer over the second SLS layer, wherein the second buffer layer has a high resistance relative to the second SLS layer; and forming a group III-V heterojunction over the second buffer layer.

13 . The method according to the claim 12 , further including:
forming the first or second SLS layer by alternatingly forming lattice mismatched layers that collectively producing a compressive force, wherein lattice mismatched layers include layers with mismatched lattice constants.

14 . The method according to claim 12 , further including:
forming the first or second SLS layers by alternatingly forming an aluminum nitride (AlN) layer and a gallium nitride (GaN) layer stacked over each other.

15 . The method according to claim 12 , further including:
forming the first or second buffer layers by forming an undoped GaN layer and doping the undoped GaN layer with carbon or iron dopants.

16 . The method according to claim 12 , further including:
forming a dielectric layer over the group III-V heterojunction; performing a first etch through source/drain regions of the dielectric layer to form source/drain openings in the dielectric layer; forming a conductive layer over the remaining dielectric layer and filling the source/drain openings; and performing a second etch through source/drain and gate regions of the conductive layer to form a gate electrode and source/drain electrodes on opposing sides of the gate electrode.

17 . The method according to claim 12 , wherein forming the group III-V heterojunction includes:
forming a channel layer over the second buffer layer; and forming an active layer over the channel layer to define a heterojunction at an interface of the channel and active layers.

18 . The method according to claim 17 , further including:
performing a first etch into a gate region of the active layer to form a first gate opening in the active layer; forming a dielectric layer over the remaining active layer and filling the first gate opening; performing a second etch into source/drain and gate regions of the dielectric layer to form source/drain openings and a second gate opening in the dielectric layer, wherein the first and second gate openings are aligned; forming a conductive layer over the remaining dielectric layer and filling the source drain and second gate openings; and performing a third etch through source/drain and gate regions of the conductive layer to form a gate electrode and source/drain electrodes on opposing sides of the gate electrode.

19 . The method according to claim 17 , further including:
forming a bottom active layer over the channel layer; performing a first etch through source/drain regions of the bottom active layer to form source/drain openings in the bottom active layer; forming a first conductive layer over the remaining bottom active layer and filling the source/drain openings; performing a second etch through source/drain regions of the first conductive layer to form source/drain electrodes; forming a top active layer and a second conductive layer stacked in that order over the remaining bottom active layer and the source/drain electrodes; and performing a third etch through a gate region of the second conductive layer and the top active layer to form a gate electrode overlying the remaining top active layer.

20 . A transistor comprising:
a silicon substrate; first and second strained layer superlattice (SLS)/buffer pairs stacked in that order over the silicon substrate, wherein the first and second SLS/buffer pairs include corresponding SLS layers and correspond

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chi-Ming
• Yu Chung-Yi
• Liu Po-Chun

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3216 Primary

  Nitrides · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D64/602

  Heterojunction gate electrodes for FETs · CPC title