Vertical cmos structure and method

Patent metadata

Field	Value
Publication number	US-2016240533-A1
Application number	US-201514640295-A
Country	US
Kind code	A1
Filing date	Mar 6, 2015
Priority date	Feb 13, 2015
Publication date	Aug 18, 2016
Grant date	—

Abstract

A method for forming stacked, complementary transistors is disclosed. Selective deposition techniques are used to form a column having a lower portion that includes one type of semiconductor (e.g. germanium) and an upper portion of another type of semiconductor (e.g. indium arsenide. The lower portion of the column provides a channel region for a transistor of one type, while the upper column provides a channel region for a transistor of another type. This provides a complementary pair that occupies a minimum of integrated circuit surface area. The complementary transistors can be utilized in a variety of circuit configurations. Described are complementary transistors where the lower transistor is p-type and the upper transistor is n-type.

First claim

1 . A complementary transistor structure comprising:
a lower portion of a column comprising a second semiconductive material formed on a substrate comprising a first semiconductor material; a first gate surrounding and insulated from the lower portion of the column; an upper portion of the column comprising a third semiconductive material; a second gate surrounding and insulated from the lower portion of the column; a first electrical contact to the upper portion of the column above the second gate; and a second electrical contact to the upper portion and lower portion of the column between the first and second gates.

2 .- 6 . (canceled)

7 . The complementary transistor structure as in claim 1 wherein the second semiconductive material is germanium.

8 . The complementary transistor structure as in claim 1 wherein the third semiconductive material is indium arsenide.

9 . A complementary transistor structure comprising:
a lower portion of a column comprising crystalline germanium formed on a silicon substrate; a first gate surrounding and insulated from the lower portion of the column; an upper portion of the column formed on top of the lower portion of the column comprising indium arsenide; a second gate surrounding and insulated from the lower portion of the column; a first electrical contact to the upper portion of the column above the second gate; and a second electrical contact to the upper portion and lower portion of the column between the first and second gates.

10 . The complementary transistor structure as in claim 9 wherein the lower portion of the column provides a channel region for a p-type field effect transistor and the upper portion of the column provides a channel region for an n-type field effect transistor.

11 . The complementary transistor structure as in claim 9 wherein the lower portion of the column provides a channel region for an n-type field effect transistor and the upper portion of the column provides a channel region for an p-type field effect transistor.

12 . The complementary transistor structure as in claim 9 wherein the first gate is insulated from the lower portion of the column by a high-k dielectric.

13 . The complementary transistor structure as in claim 9 wherein the second gate is insulated from the upper portion of the column by a high-k dielectric.

14 .- 20 . (canceled)

21 . The complementary transistor structure as in claim 1 wherein the second semiconductive material contacts the third semiconductive material.

22 . The complementary transistor structure as in claim 1 wherein the second semiconductive material is separated from the third semiconductive material.

23 . The complementary transistor structure as in claim 1 wherein the second semiconductive material and the third semiconductive material are opposite conductivity types.

24 . The complementary transistor structure as in claim 1 wherein the first gate is electrically coupled to the second gate.

25 . The complementary transistor structure as in claim 1 wherein the substrate immediately below the lower portion is electrically coupled to ground.

26 . A complementary transistor structure comprising:
a first vertical nanowire extending from a substrate, the first vertical nanowire being a first semiconductor material; a second vertical nanowire extending from the first vertical nanowire, the first vertical nanowire being disposed between the second vertical nanowire and the substrate, the second vertical nanowire being a second semiconductor material different than the first semiconductor material; a first gate adjacent a first channel region of the first vertical nanowire; and a second gate adjacent a second channel region of the second vertical nanowire, a common source/drain region being interposed between the first gate and the second gate.

27 . The complementary transistor structure of claim 26 , further comprising a gate contact electrically coupled to the first gate and the second gate.

28 . The complementary transistor structure of claim 26 , further comprising an electrical contact electrically coupled to the common source/drain region.

29 . The complementary transistor structure of claim 28 , wherein the electrical contact contacts the second vertical nanowire.

30 . The complementary transistor structure of claim 26 , wherein the first gate and the first vertical nanowire form a first transistor of a first conductivity type, the second gate and the second vertical nanowire form a second transistor of a second conductivity type, the first conductivity type being different than the second conductivity type.

31 . The complementary transistor structure of claim 26 , wherein the first semiconductor material directly contacts the second semiconductor material.

32 . The complementary transistor structure of claim 26 , further comprising a high-k dielectric material interposed between the first gate and the first vertical nanowire and interposed between the second gate and the second vertical nanowire.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Oxland Richard Kenneth

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10P14/3421

  Arsenides · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title