Interconnect structures and methods of formation

US2016240483A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016240483-A1
Application numberUS-201615041454-A
CountryUS
Kind codeA1
Filing dateFeb 11, 2016
Priority dateFeb 13, 2015
Publication dateAug 18, 2016
Grant date

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Abstract

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Interconnect structures and methods of formation of such interconnect structures are provided herein. In some embodiments, a method of forming an interconnect includes: depositing a silicon-aluminum oxynitride (SiAlON) layer atop a first layer of a substrate, wherein the first layer comprises a first feature filled with a first conductive material; depositing a dielectric layer over the silicon-aluminum oxynitride (SiAlON) layer; and forming a second feature in the dielectric layer and the silicon-aluminum oxynitride (SiAlON) layer to expose the first conductive material.

First claim

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1 . A method of forming an interconnect, comprising: depositing a silicon-aluminum oxynitride (SiAlON) layer atop a first layer of a substrate, wherein the first layer comprises a first feature filled with a first conductive material; depositing a dielectric layer over the silicon-aluminum oxynitride (SiAlON) layer; and forming a second feature in the dielectric layer and the silicon-aluminum oxynitride (SiAlON) layer to expose the first conductive material. 2 . The method of claim 1 , wherein depositing the silicon-aluminum oxynitride (SiAlON) layer comprises: sputtering an aluminum target; and sputtering a silicon target. 3 . The method of claim 2 , further comprising: simultaneously sputtering the aluminum target and the silicon target in a process chamber using a process gas comprising oxygen (O 2 ), nitrogen (N 2 ) and argon (Ar). 4 . The method of claim 2 , further comprising: sputtering the aluminum target in a first process chamber using a first process gas; transferring the substrate to a second process chamber; and sputtering the silicon target in the second process chamber using a second process gas. 5 . The method of claim 4 , wherein the first process gas comprises nitrogen (N 2 ) and argon (Ar) and the second process gas comprises one of: oxygen (O 2 ) and argon (Ar); or oxygen (O 2 ), nitrogen (N 2 ), and argon (Ar). 6 . The method of claim 4 , wherein the first process gas comprises oxygen (O 2 ) and argon (Ar) and the second process gas comprises one of: nitrogen (N 2 ) and argon (Ar); or oxygen (O 2 ), nitrogen (N 2 ), and argon (Ar). 7 . The method of claim 4 , wherein the first process gas comprises oxygen (O 2 ), nitrogen (N 2 ), and argon (Ar) and the second process gas comprises one of: oxygen (O 2 ), nitrogen (N 2 ), and argon (Ar); nitrogen (N 2 ) and argon (Ar); oxygen (O 2 ) and argon (Ar); or only argon (Ar). 8 . The method of claim 1 , wherein depositing the silicon-aluminum oxynitride (SiAlON) layer further comprises sputtering a silicon-aluminum target using a process gas comprising nitrogen (N 2 ), oxygen (O 2 ), and argon (Ar). 9 . The method of claim 8 , wherein nitrogen is provided at a flow rate of up to about 100 sccm, oxygen is provided at a flow rate of about 1 sccm to about 4 sccm, and argon is provided at a flow rate of up to about 25 sccm. 10 . The method of claim 1 , wherein depositing the silicon-aluminum oxynitride (SiAlON) layer further comprises sputtering a silicon aluminum oxynitride (SiAlON) target using a process gas comprising argon (Ar). 11 . The method of claim 1 , wherein the silicon-aluminum oxynitride (SiAlON) layer is deposited to a thickness of about 40 to about 80 angstroms. 12 . The method of claim 1 , wherein forming the second feature in the dielectric layer and the silicon-aluminum oxynitride (SiAlON) layer further comprises: depositing a photoresist layer atop the dielectric layer; patterning the photoresist layer; etching the dielectric layer to a top surface of the silicon-aluminum oxynitride (SiAlON) layer; and etching the silicon-aluminum oxynitride (SiAlON) layer to expose the first conductive material. 13 . The method of claim 12 , further comprising etching the dielectric layer using a fluorine-containing gas. 14 . The method of claim 12 , further comprising etching the silicon-aluminum oxynitride (SiAlON) layer using a wet etch process. 15 . The method of claim 1 , further comprising depositing a second conductive material to fill the second feature. 16 . An interconnect, comprising: a substrate comprising a first dielectric layer having a first feature formed in the first dielectric layer, wherein the first feature is filled with a first conductive material; a silicon aluminum oxynitride (SiAlON) layer disposed atop the first dielectric layer; a second dielectric layer disposed over the silicon aluminum oxynitride (SiAlON) layer; a second feature formed through the second dielectric layer and the silicon aluminum oxynitride (SiAlON) layer and aligned with the first feature; and a second conductive material filling the second feature to form a conductive pathway from the first feature to the second feature. 17 . The interconnect of claim 16 , wherein a thickness of the silicon aluminum oxynitride (SiAlON) layer is about 40 to about 80 angstroms. 18 . The interconnect of claim 16 , wherein the first conductive material and second conductive material are copper. 19 . A computer readable medium, having instructions stored thereon which, when executed, cause a process chamber to perform a method of forming an interconnect, the method comprising: depositing a silicon-aluminum oxynitride (SiAlON) layer atop a first layer of a substrate, wherein the first layer comprises a first feature filled with a first conductive material; depositing a dielectric layer over the silicon-aluminum oxynitride (SiAlON) layer; and forming a second feature in the dielectric layer and the silicon-aluminum oxynitride (SiAlON) layer to expose the first conductive material. 20 . The computer readable medium of claim 19 , wherein the silicon-aluminum oxynitride (SiAlON) layer is deposited to a thickness of about 40 to about 80 angstroms.

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Classifications

  • the material containing aluminium, e.g. AlSiOx · CPC title

  • using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition · CPC title

  • by forming openings in the dielectric parts · CPC title

  • on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

  • of multilayered thin functional dielectric layers · CPC title

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What does patent US2016240483A1 cover?
Interconnect structures and methods of formation of such interconnect structures are provided herein. In some embodiments, a method of forming an interconnect includes: depositing a silicon-aluminum oxynitride (SiAlON) layer atop a first layer of a substrate, wherein the first layer comprises a first feature filled with a first conductive material; depositing a dielectric layer over the silicon…
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification H10W20/425. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Aug 18 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).