Method, system and computer readable medium using stitching for mask assignment of patterns

Patent metadata

Field	Value
Publication number	US-2016240474-A1
Application number	US-201615139615-A
Country	US
Kind code	A1
Filing date	Apr 27, 2016
Priority date	May 31, 2012
Publication date	Aug 18, 2016
Grant date	—

Abstract

A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N−1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.

First claim

What is claimed is:

1 . An integrated circuit (IC), comprising:
a semiconductor substrate having at least one interconnect line layer including a plurality of circuit patterns formed of conductive material, each of the plurality of circuit patterns divided into at least N segments, where N is greater than one, the conductive material in the at least N segments having N different depths, the depths of each of the segments arranged, so that within at least one set of N circuit patterns that are parallel to each other and separated from each other by a distance smaller than a threshold distance, corresponding segments of different ones of the N circuit patterns which are adjacent to each other have different depths from each other.

2 . The IC of claim 1 , wherein:
the depths of each of the segments within each of the plurality of circuit patterns are arranged according to a sequence, so that within each set of N circuit patterns that are parallel to each other and separated from each other by a distance smaller than a threshold distance, each circuit pattern has the same sequence, and each circuit patterns has a different sequence offset from an adjacent one of the set of circuit patterns.

3 . The IC of claim 1 , further comprising at least one additional circuit pattern or portion of an additional circuit pattern, which is separated from every other circuit pattern by at least the threshold distance, the additional circuit pattern divided into at least N segments, the conductive material in the at least N segments having N different depths, the depths of each of the segments of the additional circuit pattern arranged, so that, relative to a nearest one of the plurality of circuit patterns, corresponding segments of the additional circuit pattern and the nearest circuit pattern have different depths from each other.

4 . The IC of claim 1 , wherein every circuit pattern in the interconnect line layer is divided into at least N segments, the conductive material in the at least N segments having N different depths.

5 . The IC of claim 1 , wherein the at least one interconnect line layer further comprises three circuit patterns having first and second parallel circuit patterns connected by a third circuit pattern, the third circuit pattern divided into at least two segments having different depths from each other.

6 . The IC of claim 5 , wherein the first and second parallel circuit patterns are each divided into N segments, with each pair of adjacent segments having different depths from each other.

7 . The IC of claim 1 , wherein respective totals of areas of segments having each respective depth are within a predetermined limit of each other.

8 . The IC of claim 1 , wherein the at least one interconnect line layer further comprises at least one additional parallel line separated from a nearest adjacent one of the plurality of parallel lines by a distance greater than the threshold distance, the at least one additional parallel line having at least two segments with respectively different depths from each other.

9 . The IC of claim 1 , wherein the at least one interconnect line layer further comprises a plurality of additional parallel lines, each separated from a nearest adjacent one of the plurality of parallel lines or plurality of additional parallel lines by a distance greater than the threshold distance, each of the plurality of additional parallel line having at least two segments with respectively different depths from each other.

10 . The IC of claim 9 , wherein each of the plurality of additional parallel lines has N segments with each adjacent pair of segments having respectively different depths.

11 . An integrated circuit (IC), comprising:
a semiconductor substrate having at least one interconnect line layer including a plurality of circuit patterns formed of conductive material, each of the plurality of circuit patterns divided into at least three segments having three different depths, the depths of each of the segments arranged, so that within at least one pair of circuit patterns that are parallel to each other and separated from each other by less than a threshold distance, corresponding segments of different ones of the pair of circuit patterns which are adjacent to each other have different depths from each other.

12 . The IC of claim 11 , wherein:
the depths of each of the segments within each of the plurality of circuit patterns are arranged according to a sequence, so that within each pair of circuit patterns that are parallel to each other and separated from each other by less than a threshold distance, each circuit pattern has the same sequence and a different sequence offset from an adjacent one of the set of circuit patterns.

13 . The IC of claim 11 , further comprising at least one additional circuit pattern separated from every other circuit pattern by at least the threshold distance, the conductive material in the at least three segments of the additional pattern having three different depths arranged, so that, relative to a nearest one of the plurality of circuit patterns, corresponding segments of the additional circuit pattern and the nearest circuit pattern have different depths from each other.

14 . The IC of claim 11 , wherein every circuit pattern in the interconnect line layer is divided into at least three segments having three different depths.

15 . The IC of claim 11 , wherein the at least one interconnect line layer further comprises three additional circuit patterns including:
first and second parallel circuit patterns; and a third circuit pattern connecting the first and second circuit patterns, the third circuit pattern divided into at least two segments having different depths from each other.

16 . An integrated circuit (IC), comprising:
a semiconductor substrate having at least one interconnect line layer including a plurality of circuit patterns formed of conductive material, each of the plurality of circuit patterns divided into at least three segments having three different depths, the depths of each of the segments within each of the plurality of circuit patterns are arranged according to a sequence, so that within each pair of circuit patterns in the plurality of circuit patterns, each circuit pattern has the same sequence and a different sequence offset from an adjacent one of the set of circuit patterns.

17 . The IC of claim 16 , wherein within each individual pattern, each pair of adjacent segments have respectively different depths from each other.

18 . The IC of claim 16 , wherein within each pair of circuit patterns which are adjacent to each other, each pair of adjacent segments which are parallel to each other have different depths from each other.

19 . The IC of claim 16 , wherein at least one of the circuit patterns has more than three segments.

20 . The IC of claim 16 , wherein each pair of the plurality of circuit patterns has more than three segments.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu-Tseng Hsien
• Lin Shih-Kai
• Lin Chin-Shen
• Jiang Yu-Sian
• Liu Heng-Kai
• Huang Mu-Jen
• Chen Chien-Wen

Classifications

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title