Independent power collapse methodology

Patent metadata

Field	Value
Publication number	US-2016239060-A1
Application number	US-201514622467-A
Country	US
Kind code	A1
Filing date	Feb 13, 2015
Priority date	Feb 13, 2015
Publication date	Aug 18, 2016
Grant date	—

Abstract

The feature size of semiconductor devices continues to decrease in each new generation. Smaller channel lengths lead to increased leakage currents. To reduce leakage current, some power domains within a device may be powered off (e.g., power collapsed) during periods of inactivity. However, when power is returned to the collapsed domains, circuitry in other power domains may experience significant processing overhead associated with reconfiguring communication channels to the newly powered domains. Provided in the present disclosure are exemplary techniques for isolating power domains to promote flexible power collapse while better managing the processing overhead associated with reestablishing data connections.

First claim

What is claimed is:

1 . A semiconductor device having a first processing node in a first power domain and a second processing node in a second power domain, the semiconductor device comprising:
an isolation module comprising:
a buffer located between the first and second power domains, the buffer operable to selectively provide an electrical connection between the first and second power domains;
a first logical isolation unit between the buffer and the first processing node; and
a second logical isolation unit between the buffer and the second processing node; and
an isolation sequencer operable to control the isolation module when an isolation sequence and a de-isolation sequence are performed, wherein, after the isolation sequence is performed, the first and second logical isolation units are operable to logically isolate the buffer from the first and second processing nodes, respectively, and the buffer is operable to provide electrical isolation between the first and second power domains; and wherein, after the de-isolation sequence is performed, the buffer is operable to provide communication from the first processing node to the second processing node.

2 . The semiconductor device of claim 1 , further comprising a power controller in communication with the isolation sequencer, wherein the power controller is operable to power collapse and power on the first and second power domains.

3 . The semiconductor device of claim 2 , wherein the isolation sequencer is operable to provide a busy signal to the power controller when the isolation sequence or the de-isolation sequence is being performed.

4 . The semiconductor device of claim 2 , wherein the power controller is operable to issue an isolation request to the isolation sequencer.

5 . The semiconductor device of claim 4 , wherein the isolation sequencer is operable to activate the isolation module such that the isolation sequence is performed without receiving the isolation request from the power controller.

6 . The semiconductor device of claim 1 , wherein the isolation sequencer waits for the buffer to be empty before allowing the isolation sequence to be completed.

7 . The semiconductor device of claim 2 , wherein the power controller is further operable to stop clocks associated with the first and second power domains before the isolation sequence is performed.

8 . The semiconductor device of claim 1 , wherein the buffer, the first power domain, and the second power domain are each operable to receive a distinct reset signal.

9 . The semiconductor device of claim 8 , wherein the reset signal operable to be received by the buffer is asserted when either the reset signal operable to be received by the first power domain is asserted or the reset signal operable to be received by the second power domain is asserted.

10 . The semiconductor device of claim 1 , wherein the isolation sequencer is in an always-on power domain that remains powered on whenever the semiconductor device receives power.

11 . The semiconductor device of claim 10 , wherein the isolation sequencer stores information about whether or not the first power domain is isolated from the second power domain in a memory device in the always-on power domain.

12 . The semiconductor device of claim 1 , wherein the isolation module further comprises:
a sensor associated with the first logical isolation unit, the sensor operable to generate an alert if the first processing node attempts to communicate with the second processing node during a time when the first power domain is isolated from the second power domain.

13 . The semiconductor device of claim 1 , wherein the buffer is an asynchronous First-In-First-Out (FIFO) buffer.

14 . The semiconductor device of claim 1 , wherein the second processing node is an interface or system bus.

15 . The semiconductor device of claim 14 , wherein the first processing node is operable to continue operating during a time when it is not connected to the interface or system bus.

16 . A semiconductor device having a first processing node in a first power domain and a second processing node in a second power domain, the semiconductor device comprising:
an isolation module operable to selectively enable communication from the first processing node to the second processing node, the isolation module comprising:
means for selectively providing an electrical connection between the first and second power domains; and
means for logically isolating the means for selectively providing the electrical connection from both the first processing node and the second processing node; and
means for controlling the isolation module when an isolation sequence and a de-isolation sequence are performed, wherein, after the isolation sequence is performed, the means for selectively providing the electrical connection is logically isolated from the first and second processing nodes, and electrical isolation is provided between the first and second power domains; and wherein, after the de-isolation sequence is performed, the isolation module permits communication from the first processing node to the second processing node.

17 . The semiconductor device of claim 16 , further comprising means for power collapsing and powering on the first and second power domains.

18 . The semiconductor device of claim 16 , further comprising means for providing a busy signal to the means for power collapsing and powering on the first and second power domains to indicate when the isolation sequence or the de-isolation sequence is being performed.

19 . The semiconductor device of claim 16 , further comprising means for generating an alert if the first processing node attempts to communicate with the second processing node during a time when the first power domain is isolated from the second power domain.

20 . The semiconductor device of claim 16 , wherein the means for selectively providing the electrical connection comprises an asynchronous First-In-First-Out (FIFO) buffer.

21 . The semiconductor device of claim 16 , wherein the second processing node is an interface or system bus.

22 . The semiconductor device of claim 21 , wherein the first processing node is operable to continue operating during a time when it is not connected to the interface or system bus.

23 . A non-transitory machine-readable medium having instructions stored thereon, the instructions executable by one or more processors for:
selectively providing, by a buffer between first and second power domains, an electrical connection between the first and second power domains; disabling clocks associated with the first and second power domains; isolating, by a first logical isolation unit, the buffer from a first processing node in the first power domain; isolating, by a second logical isolation unit, the buffer from a second processing node in the second power domain; enabling, within the buffer, electrical isolation between the first and second power domains; and re-enabling the clocks associated with at least one of the first and second power domains.

24 . The non-transitory machine-readable medium of claim 23 , wherein the instructions are further executable by the one or more processors for:
storing, by a memory device in an always-on power domain, information indicating whether or not the first power domain is isolated from the second power domain.

25 . The non-transitory m

Assignees

• Qualcomm Inc

Inventors

• Koob Christopher Edward
• Chen Xufeng
• Lester Robert Allan
• Pyla Manojkumar
• Zhong Peixin

Classifications

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/3237 Primary

  by disabling clock generation or distribution · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• H03K19/0016

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title