Liquid crystal display device

Patent metadata

Field	Value
Publication number	US-2016238909-A1
Application number	US-201615137340-A
Country	US
Kind code	A1
Filing date	Apr 25, 2016
Priority date	Sep 7, 1999
Publication date	Aug 18, 2016
Grant date	—

Abstract

A liquid crystal display includes a first substrate and a second substrate opposed to each other with a liquid crystal layer between the first substrate and the second substrate. The first substrate has a plurality of drain signal lines and a plurality of gate signal lines, and a plurality of pixel regions are defined by the drain signal lines and the gate signal lines. Each of the pixel regions includes a first electrode having a plurality of strip-like portions extending in an extension direction of the drain signal lines, the strip-like portions having at least one bent portion so that extension directions of each two parts of the strip-like portions separated by the at least one bent portion are different from each other, and a second electrode formed between the first substrate and the first electrode, and being overlapped with the strip-like portions in plan view.

First claim

What is claimed is:

1 . A liquid crystal display comprising:
a first substrate and a second substrate opposed to each other with liquid crystal layer therebetween, the first substrate having drain signal lines and gate signal lines; TFT element connected to one of the drain signal lines and one of the gate signal lines; a pixel electrode formed of a transparent conducting layer having a slit, the pixel electrode being connected to the TFT element; a counter electrode formed of a planar transparent conducting layer, the counter electrode being disposed on the substrate; and an insulating layer interposed between the counter electrode and the pixel electrode; wherein the counter electrode is interposed between the gate signal lines and the liquid crystal layer, and the counter electrode is overlapped with a slit of the pixel electrode, the counter electrode is overlapped with the gate signal lines. The liquid crystal display according to claim 1 , wherein the counter electrode covers an entire width of one of the gate signal lines.

3 . The liquid crystal display according to claim 1 , wherein the pixel electrode is connected to the TFT element at a connection area, the counter electrode has an opening portion, and the opening portion is arranged at a position overlapping with the connection area.

4 . The liquid crystal display according to claim 3 , wherein the insulating layer has a contact hole, the pixel electrode is connected to the TFT element through the contact hole.

5 . The liquid crystal display according to claim 4 , wherein a counter voltage signal line formed of metal is formed so that the counter voltage signal line is connected to the counter electrode, and the counter voltage signal line is formed overlapping the pixel electrode and an adjacent pixel electrode.

6 . The liquid crystal display according to claim 1 , wherein at least a part of the pixel electrode is overlapped with one of the gate signal lines.

7 . The liquid crystal display according to claim 1 , wherein at least a part of the counter electrode is arranged at a position overlapping the pixel electrode and one of the gate signal lines.

8 . The liquid crystal display according to claim 1 , wherein the TFT element has a semiconductor layer, and a portion other than the TFT element has a semiconductor layer being overlapped with one of the gate signal lines.

9 . The liquid crystal display according to claim 1 , wherein the TFT element has a semiconductor layer, and a portion other than the TFT element has a semiconductor layer being overlapped with one of the drain signal lines.

10 . The liquid crystal display according to claim 1 , wherein the liquid crystal layer has mainly negative dielectric anisotropy.

11 . A liquid crystal display comprising:
a first substrate and a second substrate opposed to each other with liquid crystal layer therebetween, the first substrate having drain signal lines and gate signal lines; TFT element connected to one of the drain signal lines and one of the gate signal lines; a pixel electrode formed of a transparent conducting layer having a linear electrode, the pixel electrode being connected to the TFT element; a counter electrode formed of a planar transparent conducting layer, the counter electrode being disposed on the first substrate; and an insulating layer interposed between the counter electrode and the pixel electrode; wherein the counter electrode is interposed between the gate signal lines and the liquid crystal layer, and the counter electrode is overlapped with a linear electrode of the pixel electrode, the counter electrode is overlapped with the gate signal lines.

12 . The liquid crystal display according to claim 11 , wherein the counter electrode covers an entire width of one of the gate signal lines.

13 . The liquid crystal display according to claim 11 , wherein the pixel electrode is connected to the TFT element a connection area, the counter electrode has an opening portion, and the opening portion is arranged at a position overlapping with the connection area.

14 . The liquid crystal display according to claim 13 , wherein the insulating layer has a contact hole, the pixel electrode is connected to the TFT element through the contact hole.

15 . The liquid crystal display according to claim 14 , wherein a counter voltage signal line formed of metal is formed so that the counter voltage signal line is connected to the counter electrode, and counter voltage signal line is formed overlapping the pixel electrode and an adjacent pixel electrode.

16 . The liquid crystal display according to claim 11 , wherein at least a part of the pixel electrode is overlapped with one of the gate signal lines.

17 . The liquid crystal display according to claim 11 , wherein at least a part of the counter electrode is arranged at a position overlapping the pixel electrode and one of the gate signal lines.

18 . The liquid crystal display according to claim 11 , wherein the TFT element has a semiconductor layer, and a portion other he TFT element has a semiconductor layer being overlapped with one of the gate signal lines.

19 . The liquid crystal display according to claim 11 , wherein the TFT element has a semiconductor ayer, and
a portion other he TFT element has a semiconductor layer being overlapped with one of the drain signal lines.

20 . The liquid crystal display according to claim 11 , wherein the liquid crystal layer has mainly negative dielectric anisotropy.

Assignees

• Japan Display Inc
• Panasonic Liquid Crystal Displ

Inventors

• Ono Kikuo
• Yoneya Makoto
• Yamamoto Tsunenori
• Hirakata Junichi
• Nakayoshi Yoshiaki

Classifications

• G02F1/13458

  Terminal pads · CPC title

• G02F1/134309

  characterised by their geometrical arrangement · CPC title

• G02F1/1393

  the birefringence of the liquid crystal being electrically controlled, e.g. ECB-, DAP-, HAN-, PI-LC cells (G02F1/1396, G02F1/141 take precedence) · CPC title

• G02F2201/40

  Arrangements for improving the aperture ratio · CPC title

• G02F1/13439

  characterised by their electrical, optical, physical properties; materials therefor; method of making · CPC title