Balanced intensity differential photo detector

Patent metadata

Field	Value
Publication number	US-2016238442-A1
Application number	US-201514622158-A
Country	US
Kind code	A1
Filing date	Feb 13, 2015
Priority date	Feb 13, 2015
Publication date	Aug 18, 2016
Grant date	—

Abstract

A circuit includes a first photo detector and a second photo detector to receive a first and second light input signal, respectfully, to generate a first current output signal and second current output signal respectively in response to the respective light input signals. A current multiplier stage receives the second current output signal from the second photo detector to generate a multiplied current output signal that is greater than the magnitude of the second current output signal. A differential multiplier having a first current path receives a portion of the multiplied current output signal and a second current path that receives another portion of the multiplied current output signal. The first current path is in series with the first current output signal to facilitate balancing of currents between the first current output signal of the first photo detector and the second current output signal of the second photo detector.

First claim

What is claimed is:

1 . A circuit comprising:
a first photo detector to receive a first light input signal and to generate a first current output signal in response to the first light input signal; a second photo detector to receive a second light input signal to generate a second current output signal in response to the second light input signal; a current multiplier stage that receives the second current output signal from the second photo detector to generate a multiplied current output signal that is greater than the magnitude of the second current output signal; and a differential multiplier having a first current path that receives a portion of the multiplied current output signal and a second current path that receives another portion of the multiplied current output signal, wherein the first current path is in series with the first current output signal to facilitate balancing of currents between the first current output signal of the first photo detector and the second current output signal of the second photo detector.

2 . The circuit of claim 1 , wherein the current multiplier stage generates the multiplied current output signal at about twice the magnitude of the second current output signal based on the received second current output signal.

3 . The circuit of claim 2 , wherein the current multiplier stage includes an adjustable gain transresistance amplifier to generate the multiplied current output signal at about twice the magnitude of the second current output signal based on the received second current output signal.

4 . The circuit of claim 3 , wherein the current multiplier stage includes a differential amplifier to provide the multiplied current output signal from the adjustable gain transresistance amplifier to the input of the differential multiplier.

5 . The circuit of claim 4 , wherein the differential amplifier includes an adjustable capacitor in a feedback loop to adjust a phase of common mode photo detector signal.

6 . The circuit of claim 1 , further comprising a current total circuit (CTC) that provides a voltage output representing the total current of the first photo detector and the second photo detector.

7 . The circuit of claim 1 , further comprising a current difference circuit (CDC) that provides a voltage output representing a difference between current of the first photo detector and the second photo detector.

8 . The circuit of claim 7 , further comprising a current loop balancer (CLB) that is driven from the CDC and provides a servo feedback path to the differential multiplier to control current difference between the first and second photo detector.

9 . The circuit of claim 8 , wherein the CLB is configured as an integrator to provide a servo feedback path to the differential multiplier to control current difference between the first and second photo detector.

10 . The circuit of claim 8 , wherein the CLB receives a bias adjustment to adjust common mode rejection between the first and second photo detector at a frequency of interest.

11 . The circuit of claim 1 , further comprising a second differential multiplier to generate the current input signal to the current multiplier stage based on the second current output signal from the second photo detector, and to isolate a capacitance of the first and second photo detectors from an input to the current multiplier stage.

12 . A circuit comprising:
a first photo detector to receive a first light input signal and to generate a first current output signal in response to the first light input signal; a second photo detector to receive a second light input signal to generate a second current output signal in response to the second light input signal; a current multiplier stage that receives a current input signal derived from the second current output signal from the second photo detector to generate a multiplied current output signal that is greater than the magnitude of the second current output signal; a first differential multiplier having a first current path that receives a portion of the multiplied current output signal and a second current path that receives another portion of the multiplied current output signal, wherein the first differential multiplier balances the currents between the first current output signal of the first photo detector and the second current output signal of the second photo detector based on the multiplied current output signal and a received balance signal that controls the first current path; and a second differential multiplier to generate the current input signal to the current multiplier stage based on the second current output signal from the second photo detector, and to isolate a capacitance of the first and second photo detectors from an input to the current multiplier stage.

13 . The circuit of claim 12 , further comprising a current total circuit (CTC) that provides a voltage output representing the total current of the first photo detector and the second photo detector.

14 . The circuit of claim 12 , further comprising a current difference circuit (CDC) that provides a voltage output representing a difference between current of the first photo detector and the second photo detector.

15 . The circuit of claim 14 , further comprising a current loop balancer (CLB) that is driven from the CDC to generate the balance signal and provides a servo feedback path to the differential multiplier to control current difference between the first and second photo detector.

16 . The circuit of claim 15 , wherein the CLB receives a bias adjustment to adjust common mode rejection between the first and second photo detector at a frequency of interest.

17 . A system, comprising:
a first photo detector to receive a first light input signal and to generate a first current output signal in response to the first light input signal; a second photo detector to receive a second light input signal to generate a second current output signal in response to the second light input signal; a current multiplier stage that receives the second current output signal from the second photo detector to generate a multiplied current output signal that is greater than the magnitude of the second current output signal; a differential multiplier having a first current path that receives a portion of the multiplied current output signal and a second current path that receives another portion of the multiplied current output signal, wherein the differential multiplier balances the currents between the first current output signal of the first photo detector and the second current output signal of the second photo detector based on the multiplied current output signal; and a gyroscope to generate the first light input signal and the second light input signal based on the angular orientation of the gyroscope.

18 . The system of claim 17 , further comprising a current total circuit (CTC) that provides a voltage output representing the total current of the first photo detector and the second photo detector.

19 . The system of claim 17 , further comprising a current difference circuit (CDC) that provides a voltage output representing a difference between current of the first photo detector and the second photo detector.

20 . The system of claim 19 , further comprising a current loop balancer (CLB) that is driven from the CDC and provides a servo feedback path to the differential multiplier to control current difference between the first and second photo detector.

Assignees

• Griffith Robert C
• Northrop Grumman Systems Corp

Inventors

• Griffith Robert C

Classifications

• G01J1/4228 Primary

  arrangements with two or more detectors, e.g. for sensitivity compensation · CPC title

• G01J1/44

  Electric circuits {(for command of an exposure part G03B7/02)} · CPC title

• G01J1/0295

  Constructional arrangements for removing other types of optical noise or for performing calibration · CPC title