High Density Storage Device System

US2016234962A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016234962-A1
Application numberUS-201514618637-A
CountryUS
Kind codeA1
Filing dateFeb 10, 2015
Priority dateFeb 10, 2015
Publication dateAug 11, 2016
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

The present disclosure provides a chassis housing an increased density of smaller storage devices. The chassis houses one or more power supplies, one or more input/output modules, and hot swappable, front accessible field replaceable units. The field replaceable units have a depth that is greater than their width and height, so as to accommodate dual storage devices one in front of the other. The proximal storage device connects to a midplane of the chassis via an interposer card situated between the proximal and distal storage devices. The interposer card conditions any signals that exhibit signal integrity problems after traversing between the midplane and the interposer card. The interposer card connects to the midplane via a bridge card and a flexible connector running underneath the distal storage device. Each field replaceable unit is placed into the front end of the chassis in a vertical orientation with respect to the chassis.

First claim

Opening claim text (preview).

What is claimed is: 1 . A storage system chassis, comprising: a device enclosure comprising a vertical dimension and a horizontal dimension, wherein the horizontal dimension is greater than the vertical dimension; a plurality of field-replaceable units (FRUs) each having a first length and a proximal end and a distal end along a longitudinal axis of the FRU, a second length along a horizontal axis transverse to the longitudinal axis, and a third length along a vertical axis, the plurality of FRUs each comprising a first storage device near the proximal end and a second storage device behind the first storage device near the distal end; and a storage controller configured to control operation of the storage devices of each of the plurality of FRUs, wherein each of the plurality of FRUs is situated with the second length in parallel with the device enclosure's vertical dimension within the device enclosure. 2 . The storage system chassis of claim 1 , wherein each of the plurality of FRUs further comprises: a midplane circuit configured to connect the first and second storage devices of each FRU to the storage controller. 3 . The storage system chassis of claim 2 , wherein each of the plurality of FRUs further comprises: a bridge circuit at the distal end of the FRU configured to connect the first and second storage devices to the storage controller via the midplane; and a flexible connector having a first connection to the bridge circuit and a second connection to an interposer circuit located between the first and second storage devices, wherein the flexible connector is configured to transmit data between the bridge circuit and the first storage device. 4 . The storage system chassis of claim 3 , wherein the bridge circuit comprises: a multiplexing circuit configured to multiplex signals between the storage controller and the first and second storage devices so that the first and second storage devices appear as a single storage device to the storage controller. 5 . The storage system chassis of claim 3 , wherein the interposer circuit comprises: a circuit configured to boost attenuated signals from the storage controller directed to the first storage device. 6 . The storage system chassis of claim 1 , wherein the second length of each of the plurality of FRUs is 2U. 7 . The storage system chassis of claim 1 , further comprising: a first power supply at a distal end of the device enclosure next to a first side of the device enclosure along the horizontal dimension; and a second power supply at the distal end of the device enclosure next to a second side of the device enclosure along the horizontal dimension, wherein the storage controller comprises a first storage controller and a second controller between the first and second power supplies at the distal end of the device enclosure, the first storage controller being below the second storage controller. 8 . A field-replaceable unit, comprising: a first length, a proximal end, and a distal end along a longitudinal axis of the field-replaceable unit; a second length along a horizontal axis transverse to the longitudinal axis; a third length along a vertical axis, the third length being less than the first and second lengths; and a first storage device near the proximal end and a second storage device behind the first storage device near the distal end, wherein the field-replaceable unit is situated within a storage system chassis so that the second length is in parallel with a vertical dimension of the storage system chassis. 9 . The field-replaceable unit of claim 8 , further comprising: a bridge circuit at the distal end of the field replaceable unit configured to connect the first and second storage devices to a storage controller via a midplane in the storage system chassis. 10 . The field-replaceable unit of claim 9 , wherein the bridge circuit comprises: a multiplexing circuit configured to multiplex signals between the storage controller and the first and second storage devices so that the first and second storage devices appear as a single storage device to the storage controller. 11 . The field-replaceable unit of claim 9 , further comprising: an interposer circuit between the first and second storage devices and configured to boost attenuated signals received from the storage controller directed to the first storage device. 12 . The field-replaceable unit of claim 11 , further comprising: a flexible connector having a first connection to the bridge circuit and a second connection to the interposer circuit, wherein the flexible connector is configured to transmit data between the bridge circuit and the first storage device. 13 . The field-replaceable unit of claim 1 , further comprising: a light pipe connected between the interposer circuit and a front face of at the proximal end and configured to convey light corresponding to a storage device status of one or both of the first and second storage devices. 14 . The field-replaceable unit of claim 8 , wherein the second length of the field replaceable unit is 2U. 15 . The field-replaceable unit of claim 8 , wherein the first and second storage devices are toolless removable from the field-replaceable unit. 16 . A method comprising: placing a first storage device in a proximal end of a field replaceable unit (FRU), the field replaceable unit having a first length and the proximal end and a distal end along a longitudinal axis of the FRU, a second length along a horizontal axis transverse to the longitudinal axis, and a third length along a vertical axis; placing a second storage device in a distal end of the FRU behind the first storage device; inserting the FRU, with the second length in parallel with a device enclosure's vertical dimension, into a receiving track of the device enclosure, wherein the device enclosure comprises the vertical dimension and the horizontal dimension and the horizontal dimension is greater than the vertical dimension. 17 . The method of claim 16 , further comprising: multiplexing, at a bridge circuit located at the distal end of the FRU, a signal received from a storage controller to one or more of the first and second storage devices so that the first and second storage devices appear as a single storage device to the storage controller; and demultiplexing, at the bridge circuit, signals received from the first and second storage devices so that a combined signal is transmitted from the field replaceable unit to the storage controller. 18 . The method of claim 16 , further comprising: transmitting data between the first storage device and a bridge circuit at the distal end of the FRU by a flexible connector connected between the bridge circuit and an interposer circuit between the first and second storage devices. 19 . The method of claim 18 , further comprising: boosting a signal received from a storage controller via the bridge circuit and flexible connector. 20 . The method of claim 16 , wherein the second length of the FRU is 2U.

Assignees

Inventors

Classifications

  • G11B33/128Primary

    of the plurality of recording/reproducing devices, e.g. disk drives, onto a chassis · CPC title

  • having electrical distribution arrangements, e.g. power supply or data communications · CPC title

  • H05K7/1489Primary

    characterized by the mounting of blades therein, e.g. brackets, rails, trays (H05K7/1491 takes precedence) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2016234962A1 cover?
The present disclosure provides a chassis housing an increased density of smaller storage devices. The chassis houses one or more power supplies, one or more input/output modules, and hot swappable, front accessible field replaceable units. The field replaceable units have a depth that is greater than their width and height, so as to accommodate dual storage devices one in front of the other. T…
Who is the assignee on this patent?
Netapp Inc
What technology area does this patent fall under?
Primary CPC classification G11B33/128. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Aug 11 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).