Semiconductor device and method for producing same

Patent metadata

Field	Value
Publication number	US-2016233308-A1
Application number	US-201615098789-A
Country	US
Kind code	A1
Filing date	Apr 14, 2016
Priority date	Aug 7, 2013
Publication date	Aug 11, 2016
Grant date	—

Abstract

A semiconductor device includes a semiconductor body, having a first surface, a gate electrode structure, which includes polycrystalline silicon, of an IGFET in a first trench extending from the first surface into the semiconductor body. The device also includes a semiconductor element, which is different from the gate electrode structure of the IGFET and includes polycrystalline silicon, in a second trench extending from the first surface into the semiconductor body, wherein the polycrystalline silicon of the IGFET and of the semiconductor element different therefrom ends below a top side of an insulation layer adjoining the first surface of the semiconductor body.

First claim

1 . A semiconductor device comprising:
a semiconductor body, having a first surface, a gate electrode structure, which comprises polycrystalline silicon, of an IGFET in a first trench extending from the first surface into the semiconductor body, and a semiconductor element, which is different from the gate electrode structure of the IGFET and comprises polycrystalline silicon, in a second trench extending from the first surface into the semiconductor body,
wherein the polycrystalline silicon of the IGFET and of the semiconductor element different therefrom ends below a top side of an insulation layer adjoining the first surface of the semiconductor body.

2 . The semiconductor device as claimed in claim 1 , wherein the first trench extends via a boundary of an active cell array into an edge termination structure of the IGFET.

3 . The semiconductor device as claimed in claim 1 , wherein any polycrystalline silicon of the semiconductor device ends below the surface of the insulation layer adjoining the first surface of the semiconductor body.

4 . The semiconductor device as claimed in claim 1 , wherein the polycrystalline silicon of the IGFET and of the semiconductor element different therefrom extends maximally as far as the first surface of the semiconductor body.

5 . The semiconductor device as claimed in claim 1 , wherein the semiconductor element comprises a diode, a resistor, a capacitor, a sensor structure, a zap structure or an edge termination structure of the IGFET.

6 . The semiconductor device as claimed in claim 1 , wherein the gate electrode structure comprises a gate electrode and a gate electrode contact-making region, which is in contact with a conductive layer below the top side of the insulation layer adjoining the first surface of the semiconductor body.

7 . The semiconductor device as claimed in claim 1 , wherein the polycrystalline silicon of the gate electrode structure of the IGFET in the first trench has a planar top side.

8 . The semiconductor device as claimed in claim 1 , wherein the polycrystalline silicon in the first trench and in the second trench in each case has a planar top side, the horizontal extents of which are offset maximally by 100 nm with respect to one another.

9 . The semiconductor device as claimed in claim 8 , wherein the planar top sides lie in a common plane.

10 . The semiconductor device as claimed in claim 1 , wherein the first trench and the second trench have depths which deviate from one another maximally by 250 nm.

11 . The semiconductor device as claimed in claim 10 , wherein the first trench and the second trench have different widths.

12 . The semiconductor device as claimed in claim 1 , furthermore comprising a dielectric, which lines the walls of the first trench and of the second trench, in order to electrically insulate the polycrystalline silicon in the first trench and the second trench from the semiconductor body.

13 . A method for producing a gate electrode structure of an IGFET and of a semiconductor element, which is different from the gate electrode structure of the IGFET, in a semiconductor device, comprising:
forming a first trench for the gate electrode structure of the IGFET and a second trench for the semiconductor element in a semiconductor body, applying polycrystalline silicon on the surface of the semiconductor body until the first trench and the second trench are filled, carrying out a chemical mechanical polishing step in order to remove polycrystalline silicon present above the first trench and the second trench, such that the polycrystalline silicon of the gate electrode structure in the first trench and the polycrystalline silicon of the semiconductor element in the second trench are separated from one another.

14 . The method as claimed in claim 13 , wherein the first trench for the gate electrode structure of the IGFET is produced in such a way that it extends via a boundary of an active cell array into an edge termination structure of the IGFET.

15 . The method as claimed in claim 13 , furthermore comprising the step of forming an insulation layer on the surface of the semiconductor body after carrying out the chemical mechanical polishing step.

16 . The method as claimed in claim 15 , further comprising forming contact holes in the insulation layer and forming a conductive layer for making contact with the polycrystalline silicon of the gate electrode structure of the IGFET and the polycrystalline silicon of the semiconductor element.

17 . The method as claimed in claim 13 , furthermore comprising forming a dielectric in the first trench and in the second trench before applying polycrystalline silicon, wherein the dielectric lines the walls of the first trench and of the second trench.

18 . The method as claimed in any of claim 13 , wherein the first trench and the second trench are formed simultaneously.

19 . The method as claimed in claim 13 , wherein any acts after carrying out the chemical mechanical polishing step are different from the act of applying polycrystalline silicon.

20 . The method as claimed in claim 13 , further comprising forming a diode, a resistor, a capacitor, a sensor structure, a zap structure or an edge termination structure of the IGFET as a semiconductor element in the second trench.

21 . The method as claimed in claim 13 , further comprising introducing dopants into the polycrystalline silicon in the second trench for the purpose of forming the semiconductor element in the second trench.

Assignees

• Infineon Technologies Ag

Inventors

• Wood Andrew Christopher Graeme
• Blank Oliver
• Poelzl Martin
• Vielemeyer Martin

Classifications

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D8/00

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title

• H10D1/43

  Resistors having PN junctions · CPC title