Semiconductor device including a semiconductor sheet unit interconnecting a source and a drain

US2016233302A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016233302-A1
Application numberUS-201615132330-A
CountryUS
Kind codeA1
Filing dateApr 19, 2016
Priority dateJun 24, 2014
Publication dateAug 11, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a substrate, a pair of source/drain units, and a semiconductor sheet unit. The substrate includes a well region. The source/drain units are disposed above the well region. The semiconductor sheet unit is disposed substantially vertically, interconnects the source/drain units, and defines a cross-sectional shape unit in a top view. The cross-sectional shape unit includes a plurality of cross-sections that have substantially the same shape and different sizes.

First claim

Opening claim text (preview).

What is claimed is: 1 . A semiconductor device comprising: a substrate including a well region; a pair of source/drain units disposed above the well region; and a semiconductor sheet unit disposed substantially vertically, interconnecting the source/drain units, and defining a cross-sectional shape unit in a top view, wherein the cross-sectional shape unit includes a plurality of cross-sections that have substantially the same shape and different sizes. 2 . The semiconductor device of claim 1 , wherein each of the cross sections is a generally straight line cross section. 3 . The semiconductor device of claim 1 , wherein each of the cross sections includes a pair of straight lines that define an angle therebetween. 4 . The semiconductor device of claim 1 , wherein each of the cross sections is curved. 5 . The semiconductor device of claim 1 , wherein the substrate further includes a second well region that has a conductivity type different from a conductivity type of the well region, the semiconductor device further comprising: a pair of second source/drain units disposed above the second well region; and a second semiconductor sheet unit disposed substantially vertically and interconnecting the second source/drain units. 6 . The semiconductor device of claim 5 , wherein the second semiconductor sheet unit defines in the top view a cross-sectional shape unit different from the cross-sectional shape unit of the semiconductor sheet unit. 7 . The semiconductor device of claim 1 , further comprising a gate stack surrounding the semiconductor sheet unit. 8 . A semiconductor device comprising: a substrate including a well region; a pair of source/drain units disposed above the well region; and a semiconductor sheet unit disposed substantially vertically, interconnecting the source/drain units, and defining a cross-sectional shape unit in a top view, wherein the cross-sectional shape unit includes a plurality of cross-sections that have different shapes. 9 . The semiconductor device of claim 8 , wherein one of the cross sections is a generally straight line cross section. 10 . The semiconductor device of claim 8 , wherein one of the cross sections includes a pair of straight lines that define an angle therebetween. 11 . The semiconductor device of claim 8 , wherein one of the cross sections is curved. 12 . The semiconductor device of claim 8 , wherein the substrate further includes a second well region that has a conductivity type different from a conductivity type of the well region, the semiconductor device further comprising: a pair of second source/drain units disposed above the second well region; and a second semiconductor sheet unit disposed substantially vertically and interconnecting the second source/drain units. 13 . The semiconductor device of claim 12 , wherein the second semiconductor sheet unit defines in the top view a cross-sectional shape unit different from the cross-sectional shape unit of the semiconductor sheet unit. 14 . The semiconductor device of claim 8 , further comprising a gate stack surrounding the semiconductor sheet unit. 15 . A semiconductor device comprising: a substrate including a well region; a pair of source/drain units disposed above the well region; and a semiconductor sheet unit disposed substantially vertically, interconnecting the source/drain units, and defining in a top view a cross-sectional shape other than a straight line. 16 . The semiconductor device of claim 15 , wherein the cross-sectional shape includes a pair of straight lines that define an angle therebetween. 17 . The semiconductor device of claim 15 , wherein the cross-sectional shape is curved. 18 . The semiconductor device of claim 15 , wherein the substrate further includes a second well region that has a conductivity type different from a conductivity type of the well region, the semiconductor device further comprising: a pair of second source/drain units disposed above the second well region; and a second semiconductor sheet unit disposed substantially vertically and interconnecting the second source/drain units. 19 . The semiconductor device of claim 18 , wherein the second semiconductor sheet unit defines in the top view a cross-sectional shape different from the cross-sectional shape of the semiconductor sheet unit. 20 . The semiconductor device of claim 15 , further comprising a gate stack surrounding the semiconductor sheet unit.

Assignees

Inventors

Classifications

  • the components including vertical IGFETs · CPC title

  • the components including insulated gates, e.g. IGFETs · CPC title

  • using silicon technology, e.g. SiGe · CPC title

  • H10D84/017Primary

    Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

  • characterised by their top-view geometrical layouts · CPC title

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What does patent US2016233302A1 cover?
A semiconductor device includes a substrate, a pair of source/drain units, and a semiconductor sheet unit. The substrate includes a well region. The source/drain units are disposed above the well region. The semiconductor sheet unit is disposed substantially vertically, interconnects the source/drain units, and defines a cross-sectional shape unit in a top view. The cross-sectional shape unit i…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D84/017. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Aug 11 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).