Semiconductor device

Patent metadata

Field	Value
Publication number	US-2016233252-A1
Application number	US-201615098787-A
Country	US
Kind code	A1
Filing date	Apr 14, 2016
Priority date	Nov 6, 2009
Publication date	Aug 11, 2016
Grant date	—

Abstract

A solid-state image sensor which holds a potential for a long time and includes a thin film transistor with stable electrical characteristics is provided. When the off-state current of a thin film transistor including an oxide semiconductor layer is set to 1×10 −13 A or less and the thin film transistor is used as a reset transistor and a transfer transistor of the solid-state image sensor, the potential of the signal charge storage portion is kept constant, so that a dynamic range can be improved. When a silicon semiconductor which can be used for a complementary metal oxide semiconductor is used for a peripheral circuit, a high-speed semiconductor device with low power consumption can be manufactured.

First claim

1 . (canceled)

2 . A semiconductor device comprising:
a photoelectric conversion element; a first transistor; a second transistor; and a third transistor, wherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor, wherein the gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the third transistor, wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a first line, wherein a gate electrode of the second transistor is electrically connected to a second line, wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the photoelectric conversion element, wherein a gate electrode of the third transistor is electrically connected to a third line, wherein the photoelectric conversion element is electrically connected to the gate electrode of the first transistor through the second transistor so that the gate electrode of the first transistor is capable of storing electrical charge, and wherein a channel of the first transistor comprises an oxide semiconductor layer.

3 . The semiconductor device according to claim 2 , wherein off-state current per micrometer of a channel width of the first transistor is 100 aA/μm or less under conditions that a source-drain voltage is 6 V and a temperature is 120° C.

4 . The semiconductor device according to claim 2 , wherein off-state current of the first transistor is 1×10 −13 A or less at a drain voltage of 1 V to 10 V.

5 . The semiconductor device according to claim 2 , wherein the oxide semiconductor layer comprises In, Ga, and Zn.

6 . The semiconductor device according to claim 2 , wherein a carrier concentration in the oxide semiconductor layer is lower than 1×10 14 /cm 3 .

7 . The semiconductor device according to claim 2 , further comprising an interlayer insulating film,
wherein the interlayer insulating film is over the photoelectric conversion element, and wherein the third transistor is over the interlayer insulating film.

8 . The semiconductor device according to claim 2 , wherein the photoelectric conversion element comprises crystalline silicon.

9 . A semiconductor device comprising:
a photoelectric conversion element; a first transistor; a second transistor; and a third transistor, wherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor, wherein the gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the third transistor, wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a first line, wherein a gate electrode of the second transistor is electrically connected to a second line, wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the photoelectric conversion element, wherein a gate electrode of the third transistor is electrically connected to a third line, wherein the photoelectric conversion element is electrically connected to the gate electrode of the first transistor through the second transistor so that the gate electrode of the first transistor is capable of storing electrical charge, wherein a channel of the first transistor comprises a first oxide semiconductor layer, and wherein a channel of the third transistor comprises a second oxide semiconductor layer.

10 . The semiconductor device according to claim 9 , wherein off-state current per micrometer of a channel width of the first transistor is 100 aA/μm or less under conditions that a source-drain voltage is 6 V and a temperature is 120° C.

11 . The semiconductor device according to claim 9 , wherein off-state current of the first transistor is 1×10 −13 A or less at a drain voltage of 1 V to 10 V.

12 . The semiconductor device according to claim 9 , wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises In, Ga, and Zn.

13 . The semiconductor device according to claim 9 , wherein a carrier concentration in the first oxide semiconductor layer is lower than 1×10 14 /cm 3 .

14 . The semiconductor device according to claim 9 , further comprising an interlayer insulating film,
wherein the interlayer insulating film is over the photoelectric conversion element, and wherein the third transistor is over the interlayer insulating film.

15 . The semiconductor device according to claim 9 , wherein the photoelectric conversion element comprises crystalline silicon.

16 . A semiconductor device comprising:
a photoelectric conversion element; a first transistor; a second transistor; and a third transistor, wherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor, wherein the gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the third transistor, wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a first line, wherein a gate electrode of the second transistor is electrically connected to a second line, wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the photoelectric conversion element, wherein a gate electrode of the third transistor is electrically connected to a third line, wherein the photoelectric conversion element is electrically connected to the gate electrode of the first transistor through the second transistor so that the gate electrode of the first transistor is capable of storing electrical charge, and wherein a channel of the third transistor comprises an oxide semiconductor layer.

17 . The semiconductor device according to claim 16 , wherein off-state current per micrometer of a channel width of the third transistor is 100 aA/μm or less under conditions that a source-drain voltage is 6 V and a temperature is 120° C.

18 . The semiconductor device according to claim 16 , wherein off-state current of the third transistor is 1×10 −13 A or less at a drain voltage of 1 V to 10 V.

19 . The semiconductor device according to claim 16 , wherein the oxide semiconductor layer comprises In, Ga, and Zn.

20 . The semiconductor device according to claim 16 , wherein a carrier concentration in the oxide semiconductor layer is lower than 1×10 14 /cm 3 .

21 . The semiconductor device according to claim 16 , further comprising an interlayer insulating film,
wherein the interlayer insulating film is over the photoelectric conversion element, and wherein the third transistor is over the interlayer insulating film.

22 . The semiconductor device according to claim 16 , wherein the photoelectric conversion element comprises crystalline silicon.

23 . A semiconductor device comprising:
a photoelectric conversion element; a first transistor; and a second transistor, wherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor, wherein the other of the source electrode and the drain electrode of the secon

Assignees

• Semiconductor Energy Lab

Inventors

• Koyama Jun
• Yamazaki Shunpei

Classifications

• H04N25/778

  comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself · CPC title

• H10D30/673

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10F30/15

  comprising amorphous semiconductors · CPC title

• H10D30/6756

  Amorphous oxide semiconductors · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title