Selective conductive barrier layer formation

Patent metadata

Field	Value
Publication number	US-2016233126-A1
Application number	US-201615133040-A
Country	US
Kind code	A1
Filing date	Apr 19, 2016
Priority date	Feb 28, 2014
Publication date	Aug 11, 2016
Grant date	—

Abstract

A semiconductor device includes a die having a via coupling a first interconnect layer to a trench. The semiconductor device also includes a barrier layer on sidewalls and adjacent surfaces of the trench, and on sidewalls of the via. The semiconductor device has a doped conductive layer on a surface of the first interconnect layer. The doped conductive layer extends between the sidewalls of the via. The semiconductor device further includes a conductive material on the barrier layer in both the via and the trench. The conductive material is on the doped conductive layer disposed on the surface of the first interconnect layer.

First claim

What is claimed is:

1 . A method of fabricating a semiconductor device comprising:
depositing a conductive oxygen scavenging layer on sidewalls and adjacent surfaces of a trench and on the sidewalls of a via opening of a die, in which the via opening exposes a first interconnect layer through the trench, and the sidewalls of the via opening including the sidewalls of a first oxide layer, the sidewalls of a cap layer and the sidewalls of a doped intermediate layer; applying a thermal treatment to the conductive oxygen scavenging layer to form a treated barrier layer on portions other than those contacting the first interconnect layer, the treated barrier layer including a first sidewall portion and a second sidewall portion directly on a surface of the first interconnect layer; and depositing a conductive material on the treated barrier layer in both the via and the trench, the conductive material being directly on the surface of a doped conductive layer disposed on the surface of the first interconnect layer and extending between the first sidewall portion and the second sidewall portion of the treated barrier layer on the opposing sidewalls of the via.

2 . The method of claim 1 , in which depositing the conductive oxygen scavenging layer is performed using atomic layer deposition.

3 . The method of claim 1 , in which depositing the conductive oxygen scavenging layer is performed using chemical vapor deposition.

4 . The method of claim 1 , in which applying the thermal treatment is performed by an in-situ thermal treatment at less than approximately 400° Celsius.

5 . The method of claim 1 , in which depositing the conductive material is performed using atomic layer deposition.

6 . The method of claim 1 , in which depositing the conductive material comprises:
depositing a conductive oxide layer using atomic layer deposition; and applying a plasma treatment to convert the conductive oxide layer into the conductive oxygen scavenging layer.

7 . The method of claim 1 , further comprising incorporating the semiconductor device into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

8 . A method of fabricating a semiconductor device comprising:
a step for depositing a conductive oxygen scavenging layer on sidewalls and adjacent surfaces of a trench and on the sidewalls of a via opening of a die, in which the via opening exposes a first interconnect layer through the trench, and the sidewalls of the via opening including the sidewalls of a first oxide layer, the sidewalls of a cap layer and the sidewalls of a doped intermediate layer; a step for applying a thermal treatment to the conductive oxygen scavenging layer to form a treated barrier layer on portions other than those contacting the first interconnect layer, the treated barrier layer including a first sidewall portion and a second sidewall portion directly on a surface of the first interconnect layer; and a step for depositing a conductive material on the treated barrier layer in both the via and the trench, the conductive material being directly on the surface of a doped conductive layer disposed on the surface of the first interconnect layer and extending between the first sidewall portion and the second sidewall portion of the treated barrier layer on the opposing sidewalls of the via.

9 . The method of claim 8 , in which the step for depositing the conductive oxygen scavenging layer is performed using atomic layer deposition.

10 . The method of claim 8 , in which the step for depositing the conductive oxygen scavenging layer is performed using chemical vapor deposition.

11 . The method of claim 8 , in which the step for applying the thermal treatment is performed by an in-situ thermal treatment at less than approximately 400° Celsius.

12 . The method of claim 8 , in which the step for depositing the conductive material is performed using atomic layer deposition.

13 . The method of claim 8 , in which the step for depositing the conductive material comprises:
depositing a conductive oxide layer using atomic layer deposition; and applying a plasma treatment to convert the conductive oxide layer into the conductive oxygen scavenging layer.

14 . The method of claim 8 , further comprising the step for incorporating the semiconductor device into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

15 . A method of fabricating a semiconductor die comprising:
exposing a first interconnect layer though an intermediate doped layer on a first oxide layer, a cap layer on the intermediate doped layer, and a second oxide layer on the cap layer; depositing a conductive oxygen scavenging layer on sidewalls and adjacent surfaces of a trench in the second oxide layer and on the sidewalls of a via opening in the second oxide layer and through the cap layer and the intermediate doped layer and landing on the first interconnect layer, in which the via opening exposes the first interconnect layer through the trench; applying a thermal treatment to the conductive oxygen scavenging layer to form a treated barrier layer on portions other than those contacting the first interconnect layer, the treated barrier layer including a first sidewall portion and a second sidewall portion directly on a surface of the first interconnect layer; and depositing a conductive material on the treated barrier layer in both the via and the trench, the conductive material being directly on the surface of a doped conductive layer disposed on the surface of the first interconnect layer and extending between the first sidewall portion and the second sidewall portion of the treated barrier layer on the opposing sidewalls of the via.

16 . The method of claim 15 , in which depositing the conductive oxygen scavenging layer is performed using atomic layer deposition.

17 . The method of claim 15 , in which depositing the conductive oxygen scavenging layer is performed using chemical vapor deposition or atomic layer deposition.

18 . The method of claim 15 , in which applying the thermal treatment is performed by an in-situ thermal treatment at less than approximately 400° Celsius.

19 . The method of claim 15 , in which depositing the conductive material comprises:
depositing a conductive oxide layer using atomic layer deposition; and applying a plasma treatment to convert the conductive oxide layer into the conductive oxygen scavenging layer.

20 . The method of claim 15 , further comprising incorporating the semiconductor die into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

Assignees

• Qualcomm Inc

Inventors

• Xu Jeffrey Junhao
• Zhu John Jianhong
• Yeap Choh Fei

Classifications

• H10W20/0526

  by thermal treatment thereof · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/049

  by diffusing alloying elements · CPC title