Method of driving a display device

Patent metadata

Field	Value
Publication number	US-2016232841-A1
Application number	US-201615016011-A
Country	US
Kind code	A1
Filing date	Feb 4, 2016
Priority date	Feb 10, 2015
Publication date	Aug 11, 2016
Grant date	—

Abstract

A method of driving a display device with a plurality of pixels including a video signal wire, a first power supply wire supplied with a first potential, a second power supply wire supplied with a second potential different to the first potential, a light emitting element arranged between the first power supply wire and the second power supply wire, a drive transistor controlling a value of a current supplied to the light emitting element, and a switch arranged between the video signal wire and the drive transistor, and inputting a signal of the video signal wire to a gate terminal of the drive transistor, wherein a minimum gradation level potential is supplied to the video signal wire after a video signal is written to the capacitor of an Nth row pixel until a video signal is written to the capacitor of an Mth (N<M) row pixel.

First claim

What is claimed is:

1 . A method of driving a display device arranged with a display part including a plurality of pixels comprising:
at least one pixel of the plurality of pixels includes a video signal wire; a first power supply wire supplied with a first potential; a second power supply wire supplied with a second potential different to the first potential; a light emitting element arranged between the first power supply wire and the second power supply wire; a drive transistor arranged between the first power supply wire and the light emitting element, and controlling a value of a current supplied to the light emitting element; a switch arranged between the video signal wire and a gate terminal of the drive transistor, and inputting a signal of the video signal wire to the gate terminal of the drive transistor; and a capacitor arranged between the gate terminal and a source terminal of the drive transistor; a minimum gradation level potential is supplied to the video signal wire after a video signal is written to the capacitor of an Nth row pixel until a video signal is written to the capacitor of an Mth (N<M) row pixel.

2 . The method of driving a display device according to claim 1 , wherein the minimum gradation level potential is a potential lower than a potential added with 0.5V to a potential corresponding to a minimum gradation.

3 . The method of driving a display device according to claim 1 , wherein the minimum gradation level potential is a potential of 0.5V or less.

4 . The method of driving a display device according to claim 1 , wherein the switch connected to the video signal wire is maintained in an OFF state while the minimum gradation level potential is supplied to the video signal wire.

5 . The method of driving a display device according to claim 1 , wherein the minimum gradation level potential is supplied to a plurality of rows with respect to the video signal wire.

6 . A method of driving a display device arranged with a display part including a plurality of pixels comprising:
at least one pixel of the plurality of pixels includes a video signal wire; a first power supply wire is supplied mutually exclusively with a first potential or a second potential different to the first potential; a second power supply wire supplied with a third potential different to the first potential and second potential; a light emitting element arranged between the first power supply wire and the second power supply wire; a drive transistor arranged between the first power supply wire and the light emitting element, and controlling a value of a current supplied to the light emitting element; a switch arranged between the video signal wire and a gate terminal of the drive transistor, and inputting a signal of the video signal wire to the gate terminal of the drive transistor; and a capacitor arranged between the gate terminal and a source terminal of the drive transistor; a minimum gradation level potential is supplied to the video signal wire after a video signal is written to the capacitor of an Nth row pixel until a video signal is written to the capacitor of an Mth (N<M) row pixel.

7 . The method of driving a display device according to claim 6 , wherein the minimum gradation level potential is a potential lower than a potential added with 0.5V to a potential corresponding to a minimum gradation.

8 . The method of driving a display device according to claim 6 , wherein the minimum gradation level potential is a potential of 0.5V or less.

9 . The method of driving a display device according to claim 6 , wherein the switch connected to the video signal wire is maintained in an OFF state while the minimum gradation level potential is supplied to the video signal wire.

10 . The method of driving a display device according to claim 6 , wherein the minimum gradation level potential is supplied to a plurality of rows with respect to the video signal wire.

11 . The method of driving a display device according to claim 6 , wherein a reset operation or offset cancel operation is performed while an initial potential is supplied to the video signal wire, and the minimum gradation level potential is supplied to the video signal wire between the reset operation and offset cancel operation.

12 . The method of driving a display device according to claim 11 , wherein the reset operation and offset cancel operation are performed collectively for a plurality of rows.

13 . The method of driving a display device according to claim 12 , wherein the minimum gradation level potential is supplied to the video signal wire after a video signal is written to the capacitor of the Nth row pixel until a video signal is written to the capacitor of an N+1th row pixel.

14 . The method of driving a display device according to claim 11 , wherein the minimum gradation level potential is supplied to the video signal wire after the initial potential is written to the capacitor of the Nth row pixel until the initial potential is written to the capacitor of an Mth (N<M) row pixel.

Assignees

• Japan Display Inc

Inventors

• Umeda Yutaka
• PENG Duzen
• Wu Ilin
• Shibusawa Makoto
• Kimura Hiroyuki

Classifications

• G09G2310/0254

  Control of polarity reversal in general, other than for liquid crystal displays · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2320/0214

  with crosstalk due to leakage current of pixel switch in active matrix panels · CPC title