Semiconductor structure and method for manufacturing the same

US2016229692A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016229692-A1
Application numberUS-201514643183-A
CountryUS
Kind codeA1
Filing dateMar 10, 2015
Priority dateFeb 6, 2015
Publication dateAug 11, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a base substrate and a MEMS structure. The base substrate comprises a CMOS structure. The MEMS structure is formed on the base substrate adjacent to the CMOS structure. The MEMS structure is connected to the CMOS structure. The MEMS structure comprises a membrane and a backplate. The base substrate has a cavity corresponding to the MEMS structure.

First claim

Opening claim text (preview).

What is claimed is: 1 . A semiconductor structure, comprising: a base substrate comprising a CMOS structure; and a MEMS structure formed on the base substrate adjacent to the CMOS structure, wherein the MEMS structure is connected to the CMOS structure, and the MEMS structure comprises: a membrane made of doped polysilicon; and a backplate; wherein the base substrate has a cavity corresponding to the MEMS structure. 2 . The semiconductor structure according to claim 1 , wherein the backplate has a plurality of through holes, and the backplate comprises an electrode layer and a support layer supporting the electrode layer. 3 . The semiconductor structure according to claim 1 , wherein the MEMS structure further comprises: an air gap between the membrane and the backplate. 4 . The semiconductor structure according to claim 1 , further comprising: vias and a conductive layer formed above the MEMS structure and the CMOS structure, wherein the membrane and the backplate are connected to the CMOS structure by the vias and the conductive layer. 5 . A method for manufacturing a semiconductor structure, comprising: providing a base substrate and a temporary substrate, wherein the base substrate comprises a CMOS structure, and the temporary substrate comprises a carrier layer, a membrane layer, and a backplate for a MEMS structure; bonding the temporary substrate with the base substrate; forming a membrane for the MEMS structure by patterning the membrane layer; connecting the membrane and the backplate to the CMOS structure; and forming a cavity corresponding to the MEMS structure in the base substrate. 6 . The method according to claim 5 , wherein forming the membrane is carried out before bonding the temporary substrate with the base substrate, and the method further comprises: after bonding the temporary substrate with the base substrate, removing the carrier layer. 7 . The method according to claim 5 , wherein forming the membrane is carried out after bonding the temporary substrate with the base substrate, and the method further comprises: after bonding the temporary substrate with the base substrate and before forming the membrane, removing the carrier layer. 8 . The method according to claim 5 , wherein the membrane layer is made of doped polysilicon. 9 . The method according to claim 5 , wherein the backplate has a plurality of through holes, the backplate comprises an electrode layer and a support layer supporting the electrode layer. 10 . The method according to claim 9 , wherein before forming the cavity, the through holes are plugged up by an oxide, and the oxide is removed at the same step of forming an air gap for the MEMS structure. 11 . The method according to claim 5 , wherein the temporary substrate further comprises a sacrificial layer between the membrane layer and the backplate, and the method further comprises: forming an air gap for the MEMS structure by removing a part of the sacrificial layer. 12 . The method according to claim 5 , wherein the membrane and the backplate are connected to the CMOS structure by vias and a conductive layer above the MEMS structure and the CMOS structure. 13 . The method according to claim 12 , further comprising: forming a hard mask layer on the conductive layer, wherein the hard mask layer has an opening corresponding to the MEMS structure. 14 . The method according to claim 5 , further comprising: before forming the cavity, forming a protective layer over the MEMS structure and the CMOS structure, thinning a base of the base substrate, and forming an opening in the base, wherein the cavity is formed by extending the opening.

Assignees

Inventors

Classifications

  • Diaphragms, membranes (manufacture process for semi-permeable inorganic membranes B01D67/0039) · CPC title

  • Transducers for transforming electrical into mechanical energy or vice versa (dynamo-electric machines H02K99/00; electrostatic machines H02N1/00; piezoelectric devices H10N30/00) · CPC title

  • Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function · CPC title

  • Forming interconnections between the electronic processing unit and the micromechanical structure · CPC title

  • Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure · CPC title

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What does patent US2016229692A1 cover?
A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a base substrate and a MEMS structure. The base substrate comprises a CMOS structure. The MEMS structure is formed on the base substrate adjacent to the CMOS structure. The MEMS structure is connected to the CMOS structure. The MEMS structure comprises a membrane and a backplate…
Who is the assignee on this patent?
United Microelectronics Corp
What technology area does this patent fall under?
Primary CPC classification B81C1/00158. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Thu Aug 11 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).