Inductive Load Driver Slew Rate Controller

Patent metadata

Field	Value
Publication number	US-2016226472-A1
Application number	US-201615095896-A
Country	US
Kind code	A1
Filing date	Apr 11, 2016
Priority date	Mar 9, 2013
Publication date	Aug 4, 2016
Grant date	—

Abstract

A circuit and method for digital controlling the slew rate of load voltage are provided. The circuit is comprised of a digital slew-rate control unit that utilizes a feedback signal to generate control signals where the feedback signal indicates the observed rate of voltage change on the load. The circuit is further comprised of a load driver circuit that is operated by the control signals and provides a slew-rate controlled output voltage used to operate a load switch, where the load switch provides power to the load. The circuit is configured to operate the load switch using a slew-rate controlling driver, depending on the state of the load switch transition, and a non-controlling driver.

First claim

1 . An integrated circuit for driving a first load switch wherein the first load switch powers a current load, the integrated circuit comprising:
a first digital slew-rate control unit for generating first control signals, wherein the first digital slew-rate control unit generates the first control signals based on a feedback signal that indicates the rate of voltage change on the load; and a first driver operated by the first control signals, wherein the first driver generates a slew-rate controlled output signal that operates the first load switch, wherein the first driver is modulated to generate the slew-rate controlled output signal during state transitions of the first load switch.

2 . The integrated circuit of claim 1 , wherein the first load switch is a MOSFET.

3 . The integrated circuit of claim 1 , further comprising a second driver that generates a constant output, wherein the first load switch is operated by the first driver and the second driver, and wherein the second driver generates a constant output during steady states of the first load switch

4 . The integrated circuit of claim 3 , wherein the first driver is a large low impedance driver and the second driver is a small current limited driver.

5 . The integrated circuit of claim 3 , wherein the first load switch is a low-side load switch and the integrated circuit further comprises:
a second digital slew-rate control unit for generating second control signals, wherein the second digital slew-rate control unit receives a second input signal and generates the second control signals based on the second input signal and the feedback signal that indicates the rate of voltage change on the load; and a third driver operated by the second control signals, wherein the third driver generates a slew-rate controlled output signal that operates the second load switch, a fourth driver that generates a constant output, wherein the second load switch is operated by the third driver and the fourth driver, and wherein the fourth driver generates a constant output during steady states of the second load switch, and wherein the third driver is modulated to generate a slew-rate controlled output during state transitions of the second load switch, wherein the third and fourth drivers are a high-side drivers.

6 . The integrated circuit of claim 1 , wherein the first digital slew-rate control unit comprises:
a capacitor that receives the feedback signal; and a resistor coupled with the capacitor that defines the slew rate.

7 . The integrated circuit of claim 6 , wherein the first digital slew-rate control unit further comprises:
a NAND gate having a first input receiving the feedback signal and a second input receiving an input voltage signal, wherein the output of the NAND gate controls a p-channel field-effect transistor of the first driver; and a NOR gate having a first input receiving the feedback signal and a second input receiving the input voltage signal, wherein the output of the NOR gate controls an n-channel field-effect transistor of the first driver, wherein the p-channel field-effect transistor and the n-channel field-effect transistor are coupled in series and a node between the p-channel field-effect transistor and the n-channel field-effect transistor provides an output of the first driver.

8 . A slew-rate controlled load driving system comprising:
a first load switch for powering a current load; a first digital slew-rate control unit that generates control signals, wherein the control signals are generated based on a feedback signal that indicates the rate of voltage change on the load; and a first load driver circuit operated by the control signals, wherein the first load driver circuit generates a modulated slew-rate controlled output voltage that operates the first load switch during state transitions of the first load switch.

9 . The system of claim 8 , wherein the first load switch is a MOSFET.

10 . The system of claim 9 , wherein the first digital slew-rate control unit and the first load driver circuit comprise a slew-rate control driver; and the system further comprises:
a non-control driver that generates a constant output, wherein the load switch is operated by the non-control driver and the slew-rate control driver, and wherein the slew-rate control driver generates a constant output during steady states of the load switch, and wherein the slew-rate control driver is pulse width modulated to generate the modulated slew-rate controlled output during state transitions of the first load switch.

11 . The system of claim 10 , wherein the slew-rate controlled driver is a large low impedance driver and the non-control driver is a small current limited driver.

12 . The system of claim 8 , wherein first digital slew-rate control unit and the first load driver circuit comprise a low-side driver, and the first load switch is a low-side load switch and the system further comprises:
a second digital slew-rate control unit for generating high-side control signals, wherein the second digital slew-rate control unit generates the high-side control signals based on the feedback signal that indicates the rate of voltage change on the load; a second load driver circuit operated by the high-side control signals, wherein the second load driver circuit generates a slew-rate controlled output voltage that operates the second load switch, wherein the second load driver circuit and the second digital slew-rate control unit comprise a high-side driver.

13 . The system of claim 8 , wherein the first digital slew-rate control unit further comprises:
a capacitor that receives the feedback signal; and a resistor coupled with the capacitor that defines the slew rate.

14 . The system of claim 13 , wherein the first digital slew-rate control unit further comprises:
a NAND gate having a first input receiving the feedback signal and a second input receiving an input voltage signal, wherein the output of the NAND gate controls a p-channel field-effect transistor of the first load driver circuit; and a NOR gate having a first input receiving the feedback signal and a second input receiving the input voltage signal, wherein the output of the NOR gate controls an n-channel field-effect transistor of the first load driver circuit.

15 . A method for controlling the slew rate of a first load switch, wherein the first load switch powers a current load, the method comprising:
generating, via a first digital slew-rate control unit, first control signals, wherein the first digital slew-rate control unit generates the first control signals based on a feedback signal that indicates the rate of voltage change on the load; generating a slew-rate controlled output voltage via a first driver, wherein the first driver is operated by the first control signals; and controlling the first load switch with the first driver, wherein during state transitions, the first driver is modulated.

16 . The method of claim 15 , wherein the first load switch is a MOSFET, and the method further comprises:
applying the slew-rate controlled first output voltage to the gate terminal of the MOSFET.

17 . The method claim 15 , further comprising generating a constant output depending on a first input signal using a second driver and controlling the first load switch with the first and second driver.

18 . The method of claim 17 , wherein the first driver and the second driver are low-side drivers, and the first load switch is a low-side load switch, the method further comprising:
generating, via a second digita

Assignees

• Microchip Tech Inc

Inventors

• De Geeter Bart
• Furrer Nicolas

Classifications

• H03K17/166

  Soft switching · CPC title

• H03K2217/0063

  High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load · CPC title

• H03K5/04 Primary

  by increasing duration; by decreasing duration · CPC title

• H03K17/6871

  the output circuit comprising more than one controlled field-effect transistor · CPC title

• H03K17/167

  using parallel switching arrangements · CPC title