Chip package, package substrate and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2016219714-A1
Application number	US-201514602539-A
Country	US
Kind code	A1
Filing date	Jan 22, 2015
Priority date	Jan 22, 2015
Publication date	Jul 28, 2016
Grant date	—

Abstract

A package substrate is provided. The package substrate includes: a dielectric layer; a passive component embedded in the dielectric layer and contacting the dielectric layer; and a circuit layer embedded in the dielectric layer and having a first surface aligned with a second surface of the dielectric layer.

First claim

1 . A package substrate, comprising:
a dielectric layer; a passive component embedded in the dielectric layer and contacting the dielectric layer; and a circuit layer embedded in the dielectric layer and having a first surface aligned with a second surface of the dielectric layer.

2 . The package substrate as claimed in claim 1 , wherein the passive component includes a capacitor.

3 . The package substrate as claimed in claim 1 , further comprising:
an adhesive layer adhered to the passive component.

4 . The package substrate as claimed in claim 3 , wherein the adhesive layer is disposed on a third surface of the dielectric layer, and the third surface is opposite to the second surface.

5 . The package substrate as claimed in claim 3 , wherein the adhesive layer is embedded in the dielectric layer.

6 . The package substrate as claimed in claim 5 , wherein the adhesive layer has a fourth surface aligned with the first surface of the circuit layer and the second surface of the dielectric layer.

7 . The package substrate as claimed in claim 5 , wherein the adhesive layer is adhered to both the passive component and the circuit layer, and the adhesive layer comprises a conductive material to electrically connect the passive component to the circuit layer.

8 . The package substrate as claimed in claim 3 , wherein the adhesive layer comprises an insulating material.

9 . A chip package, comprising:
a package substrate, comprising: a dielectric layer; a passive component embedded in the dielectric layer and contacting the dielectric layer; a first circuit layer embedded in the dielectric layer and having a first surface aligned with a second surface of the dielectric layer; and a chip disposed on the package substrate and electrically connected to the first circuit layer and the passive component.

10 . The chip package as claimed in claim 9 , further comprising:
an encapsulating layer disposed on the package substrate and covering the chip.

11 . The chip package as claimed in claim 9 , wherein the chip is disposed on the second surface of the dielectric layer.

12 . The chip package as claimed in claim 9 , further comprising:
a second circuit layer disposed on a third surface of the dielectric layer, wherein the third surface is opposite to the second surface; and a plurality of solder balls disposed on the second circuit layer.

13 . The chip package as claimed in claim 12 , further comprising:
an adhesive layer disposed on the third surface and adhered to the passive component; and a conductive via passing through the adhesive layer and connected to the passive component and the second circuit layer.

14 . The chip package as claimed in claim 9 , further comprising:
an adhesive layer embedded in the dielectric layer and adhered to the passive component; and a conductive via passing through the adhesive layer and connected to the passive component and the chip.

15 . The chip package as claimed in claim 9 , further comprising:
an adhesive layer disposed in the dielectric layer and between the passive component and the first circuit, wherein the adhesive layer comprises a conductive material to electrically connect the passive component to the first circuit.

16 - 20 . (canceled)

Assignees

• Mediatek Inc

Inventors

• Hsu Wen-Sung
• Yu Ta-Jen

Classifications

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W70/635 Primary

  Through-vias · CPC title