Gear shifting from binary phase detector to pam phase detector in cdr architecture

Patent metadata

Field	Value
Publication number	US-2016218859-A1
Application number	US-201514686203-A
Country	US
Kind code	A1
Filing date	Apr 14, 2015
Priority date	Jan 28, 2015
Publication date	Jul 28, 2016
Grant date	—

Abstract

A device and method for providing clock data recovery (CDR) in a receiver is disclosed. The method comprises receiving a Phase Amplitude Modulation (PAM) signal; on startup, using a non-return-to-zero (NRZ)-based phase frequency detector (PFD) to acquire signal frequency from the received PAM signal; and responsive to a determination, switching to a PAM phase detector (PD) for steady state operation.

First claim

1 - 3 . (canceled)

4 . A method for providing clock data recovery (CDR) in a receiver, the method comprising:
receiving a Phase Amplitude Modulation (PAM) signal; on startup, using a non-return-to-zero (NRZ)-based phase frequency detector (PFD) to acquire a frequency from the received PAM signal; and
responsive to a determination, switching to a PAM phase detector (PD) for steady state operation of the CDR module;
receiving at the NRZ-based PFD a first signal that comprises the received PAM signal after amplification and equalization using a continuous time linear filter;
receiving at the PAM PD a second signal that comprises the first signal summed with a correction provided by a Decision Feedback Equalizer (DFE); and
receiving at the PAM PD a third signal that comprises PAM data output from the DFE.

5 . The method as recited in claim 4 further comprising making the determination after convergence of a decision feedback equalizer (DFE).

6 . (canceled)

7 . A method for providing clock data recovery (CDR) in a receiver, the method comprising:
receiving a Phase Amplitude Modulation (PAM) signal; on startup, using a non-return-to-zero (NRZ)-based phase frequency detector (PFD) to acquire a frequency from the received PAM signal; and
responsive to a determination, switching to a PAM phase detector (PD) for steady state operation of the CDR module; and
making the determination responsive to detecting that a fixed time has elapsed since Decision Feedback Equalizer (DFE) convergence;
wherein the fixed time is greater than or equal to a given number of unit intervals (UI) of the received signal.

8 . A method for providing clock data recovery (CDR) in a receiver, the method comprising:
receiving a Phase Amplitude Modulation (PAM) signal; on startup, using a non-return-to-zero (NRZ)-based phase frequency detector (PFD) to acquire a frequency from the received PAM signal; and
responsive to a determination, switching to a PAM phase detector (PD) for steady state operation of the CDR module; and
making the determination responsive to detecting that a vertical eye opening of the second signal for a given symbol error rate (SER) is above a specified threshold.

9 . The method as recited in claim 8 wherein the SER is below 10 −3 and the threshold is less than or equal to 50% of maximum eye opening.

10 - 12 . (canceled)

13 . A clock data recovery (CDR) module comprising:
a non-return-to-zero (NRZ)-based phase frequency detector (PFD); and
a PAM phase detector (PAMPD), wherein the CDR module initiates phase and frequency acquisition using the NRZ-based PFD and responsive to a determination, switches to PAMPD for steady state operation;
wherein the NRZ-based PFD is connected to receive a first signal that comprises a received PAM signal that has been equalized by a linear equalizer and amplified by a voltage gain amplifier;
wherein the PAMPD is further connected to receive a second signal that comprises the first signal summed with a correction provided by a decision feedback equalizer (DFE); and
wherein the PAMPD is further connected to receive a third signal that comprises recognized PAM data output from the DFE.

14 . The CDR module as recited in claim 13 wherein the determination is made after frequency locking.

15 . The CDR module as recited in claim 14 wherein the determination is made after convergence of the DFE.

16 . (canceled)

17 . A clock data recovery (CDR) module comprising:
a non-return-to-zero (NRZ)-based phase frequency detector (PFD); and
a PAM phase detector (PAMPD), wherein the CDR module initiates phase and frequency acquisition using the NRZ-based PFD and responsive to a determination, switches to PAMPD for steady state operation;
wherein the determination is made responsive to detecting that a fixed time has elapsed since DFE convergence; and
wherein the fixed time is greater than or equal to a given number of unit intervals (UI) of the received signal.

18 . A clock data recovery (CDR) module comprising:
a non-return-to-zero (NRZ)-based phase frequency detector (PFD); and
a PAM phase detector (PAMPD), wherein the CDR module initiates phase and frequency acquisition using the NRZ-based PFD and responsive to a determination, switches to PAMPD for steady state operation;
wherein the determination is made responsive to detecting that a vertical eye opening of the second signal for a given symbol error rate (SER) is above a specified threshold.

19 . The CDR module as recited in claim 18 wherein the SER is below 10 −3 and the threshold is less than or equal to 50% of maximum eye opening.

20 . A receiver comprising:
a linear equalizer connected to provide a first signal, the first signal comprising a received PAM signal that has been equalized; a decision feedback equalizer (DFE) connected to receive the first signal and to provide a second signal and a third signal, the second signal comprising the first signal summed with a correction and the third signal comprising recognized PAM data; and a clock data recovery (CDR) module comprising a non-return-to-zero (NRZ)-based pulse frequency detector (PFD) and a PAM phase detector (PAMPD), the CDR module being connected to receive the first, second and third signals; wherein the CDR module initiates phase and frequency acquisition using the NRZ-based PFD and responsive to a determination, switches to PAMPD for steady state operation.

Assignees

• Texas Instruments Inc

Inventors

• Hoshyar Reza
• Zheng Kevin
• Warke Nirmal
• Kiaei Ali
• Bahai Ahmad

Classifications

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L7/0016

  correction of synchronization errors · CPC title

• H04L2025/03363

  Multilevel (H04L2025/03369 takes precedence) · CPC title

• H04L2025/03484

  time-recursive · CPC title

• H04L25/03267

  with decision feedback equalisers · CPC title