Multi-stage track-and-hold amplifier

Patent metadata

Field	Value
Publication number	US-2016218685-A1
Application number	US-201615092215-A
Country	US
Kind code	A1
Filing date	Apr 6, 2016
Priority date	Feb 12, 2014
Publication date	Jul 28, 2016
Grant date	—

Abstract

Examples are provided for a multi-stage track-and-hold circuit (THA). The multi-stage THA may include a first stage, a second stage, and a third stage. The first stage may be coupled to an input signal and configured to sample the input signal. The second stage may be coupled to the first stage and may include a buffer circuit. The third stage may be coupled to the second stage and can include a bootstrapped THA. The first stage may further include a shunted source-follower circuit and a switched source-follower circuit. The shunted source-follower circuit may include a first switch that can be operable to couple an output node of the shunted source-follower circuit to ground potential.

First claim

What is claimed is:

1 . A multi-stage track-and-hold amplifier (THA), comprising:
a first stage configured to receive an input signal and configured to sample the input signal; and a second stage coupled to the first stage and including a buffer circuit, wherein:
the first stage comprises a shunted source-follower circuit and a switched source-follower circuit,
the shunted source-follower circuit includes a first current source and a first switch,
the switched source-follower circuit includes a second current source coupled via a second switch to an output node of the switched source-follower circuit, and
the buffer circuit comprises a class-A source follower configured to present a low input-capacitance to the first stage.

2 . The multi-stage THA of claim 1 , wherein:
the shunted source-follower circuit comprises a first MOS transistor and the first current source couples a source of the first MOS transistor to a node of a first power supply, the first switch is operable to couple an output node of the shunted source-follower circuit to ground potential, the first MOS transistor comprises a PMOS transistor, when the input signal includes a low common-mode voltage, the first power supply is configured to provide a positive supply voltage, and a gate node of the first MOS transistor is coupled to the input signal and a drain node of the first MOS transistor is coupled to ground potential.

3 . The multi-stage THA of claim 2 , wherein:
the output node of the shunted source-follower circuit comprises the source of the first MOS transistor, the first switch comprises a shunt switch and is operable to couple the output node of the shunted source-follower circuit to ground potential, when the first stage is in a hold mode, to provide a reduced hold-mode feed-through and to prevent an input to the second stage from floating, the first switch is operable to be an open circuit when the first stage is in a track mode, and the first stage is in the track mode when the multi-stage THA is in a hold state.

4 . The multi-stage THA of claim 2 , wherein:
the switched source-follower circuit comprises a second MOS transistor coupled to the second switch, and the second current source, the second MOS transistor comprises an NMOS transistor where the first MOS transistor is a PMOS transistor, a gate node of the second MOS transistor is coupled to the output node of the shunted source-follower circuit, a drain node of the second MOS transistor is coupled to the node of the first power supply, the second switch is operable to couple a source node of the second MOS transistor to the second current source, the second current source is coupled to a node of a second power supply, and the second power supply is configured to provide a negative supply voltage.

5 . The multi-stage THA of claim 4 , wherein:
the second switch is operable to couple the source node of the second MOS transistor to the second current source when the first stage is in a track mode, the second switch is operable to decouple the source node of the second MOS transistor from the second current source when the first stage is in a hold mode, and the first stage is in a hold mode when the multi-stage THA is in a track state.

6 . The multi-stage THA of claim 1 , further comprising a third stage coupled to the second stage and including a track-and-hold circuit,
wherein: the buffer circuit is configured to isolate the first stage from the third stage to reduce a load on the first stage, and the buffer circuit is configured to enhance a bandwidth of the first stage and to enable an ultra-wide bandwidth for the multi-stage THA.

7 . The multi-stage THA of claim 6 , wherein:
the track-and-hold circuit of the third stage comprises a Vgs-bootstrapped track-and-hold circuit configured to process a sampled signal generated by the first stage, the Vgs-bootstrapped track-and-hold circuit includes a Vgs-bootstrapped switch configured to achieve a high-linearity performance, the Vgs-bootstrapped switch is a low-power switch, the Vgs-bootstrapped switch is operable to be closed when the third stage is in a track mode, the third stage is in the track mode when the multi-stage THA is in a track state, the third stage comprises multiple track-and-hold circuits, and each of the multiple track-and-hold circuits is configured to operate at a fraction of a sampling rate of the first stage.

8 . The multi-stage THA of claim 1 , wherein:
the buffer circuit allows parallel operation of a plurality of multi-stage THAs, and the parallel operation of the plurality of multi-stage THAs facilitates time-interleaving of multiple high-frequency input signals.

9 . A method for providing a multi-stage track-and-hold amplifier (THA), comprising:
providing a first stage to receive an input signal and configuring the first stage to sample the input signal; and coupling a second stage to the first stage, the second stage including a buffer circuit, wherein:
providing the first stage comprises providing a switched source-follower circuit,
providing the switched source-follower circuit comprises coupling a second current source via a second switch to an output node of the switched source-follower circuit, and
the buffer circuit comprises a class-A source follower configured to present a low input-capacitance to the first stage.

10 . The method of claim 9 ,
wherein:
providing the first stage comprises providing a shunted source-follower circuit,
providing the shunted source-follower circuit comprises coupling a first current source and a first switch operable to couple an output node of the shunted source-follower circuit to ground potential,
the shunted source-follower circuit comprises a first MOS transistor and the first current source,
the first MOS transistor comprises a PMOS transistor, when the input signal includes a low common-mode voltage, and
the method comprises:
coupling a source of the first MOS transistor to a node of a first power supply through the first current source;
configuring the first power supply to provide a positive supply voltage;
coupling a gate node of the first MOS transistor to the input signal; and
coupling a drain node of the first MOS transistor to ground potential.

11 . The method of claim 10 , comprising:
configuring the source of the first MOS transistor as the output node of the shunted source-follower circuit; configuring the first switch to couple the output node of the shunted source-follower circuit to ground potential, when the first stage is in a hold mode, to provide a reduced hold-mode feed-through and to prevent an input of the second stage from floating; and configuring the first switch to be an open circuit when the first stage is in a track mode, wherein the first stage is in the track mode when the multi-stage THA is in a hold state.

12 . The method of claim 10 , further comprising:
forming the switched source-follower circuit by coupling a second MOS transistor to the second switch and the second current source; coupling a gate node of the second MOS transistor to the output node of the shunted source-follower circuit; coupling a drain node of the second MOS transistor to the node of the first power supply; configuring the second switch to couple a source node of the second MOS transistor to the second current source; coupling the second current source to a node of a second power supply; and configuring the second power supply to provide a negative supply voltage, wherein the second MOS transistor comprises an NMOS transistor where the first MOS transistor is a PMOS transistor.

Assignees

• Semtech Corp

Inventors

• D'Souza Sandeep Louis
• Dyer Kenneth Colin
• Bachu Raghava Manas

Classifications

• H03F2200/297

  the loading circuit of an amplifying stage comprising a capacitor · CPC title

• H03F2200/411

  the output amplifying stage of an amplifier comprising two power stages · CPC title

• G11C27/02 Primary

  Sample-and-hold arrangements (G11C27/04 takes precedence) · CPC title

• H03F3/16 Primary

  with field-effect devices · CPC title