Chip-on-film package and display device including the same

Patent metadata

Field	Value
Publication number	US-2016218053-A1
Application number	US-201614993044-A
Country	US
Kind code	A1
Filing date	Jan 11, 2016
Priority date	Jan 26, 2015
Publication date	Jul 28, 2016
Grant date	—

Abstract

A chip-on-film (COF) package includes a base film, a semiconductor chip mounted on a chip mounting region of a top surface of the base film, a plurality of top inner output conductive patterns, a plurality of bottom inner output conductive patterns and a plurality of landing vias. The top inner output conductive patterns are formed on the top surface of the base film and respectively connected to chip inner output pads formed on a bottom surface of the semiconductor chip. The bottom inner output conductive patterns are formed on a bottom surface of the base film. The landing vias are formed to vertically penetrate the base film and to respectively connect the top inner output conductive patterns and the bottom inner output conductive patterns. The landing vias are arranged within the chip mounting region to form a two-dimensional shape.

First claim

What is claimed is:

1 . A chip-on-film (COF) package comprising:
a base film; a semiconductor chip mounted on a chip mounting region of a top surface of the base film; a plurality of top inner output conductive patterns formed on the top surface of the base film and respectively connected to chip inner output pads formed on a bottom surface of the semiconductor chip; a plurality of bottom inner output conductive patterns formed on a bottom surface of the base film; and a plurality of landing vias formed to penetrate the base film and to respectively connect the top inner output conductive patterns and the bottom inner output conductive patterns, the landing vias arranged within the chip mounting region to form a two-dimensional shape.

2 . The COF package of claim 1 , wherein the landing vias are arranged to form at least one triangular shape.

3 . The COF package of claim 1 , wherein the chip mounting region has a rectangular shape with first and second long sides along a first direction and first and second short sides along a second direction perpendicular to the first direction, and the chip mounting region includes an output pad region adjacent to the first long side, an input pad region adjacent to the second long side and a landing via region between the output pad region and the input pad region.

4 . The COF package of claim 3 , wherein the landing via region includes a plurality of sub-regions arranged along the first direction, and the sub-regions have a same arrangement of the landing vias.

5 . The COF package of claim 3 , wherein the landing via region includes a plurality of sub-regions arranged along the first direction, and two adjacent sub-regions have a symmetric arrangement of the landing vias with respect to a boundary line of the two adjacent sub-regions.

6 . The COF package of claim 3 , wherein the top inner output conductive patterns include:
a plurality of inner output pads arranged along the first direction within the output pad region; a plurality of top landing via pads arranged on the landing vias within the landing via region; and a plurality of inner connection lines respectively connecting the inner output pads and the top landing via pads.

7 . The COF package of claim 6 , wherein at least two landing vias connected to at least two adjacent inner output pads are adjacent and arranged along the first direction.

8 . The COF package of claim 7 , wherein at least one inner connection line among the inner connection lines connected to the at least two landing vias includes a first line and a second line, the first line connected to the corresponding top landing via pad and extended along the first direction, the second line connecting the first line and the corresponding inner output pad and extended along the second direction.

9 . The COF package of claim 3 , wherein the bottom inner output conductive patterns include:
a plurality of bottom landing via pads arranged beneath the landing vias within the landing via region; and a plurality of inner output lead lines respectively connected to the bottom landing via pads and extended along the second direction across the first long side of the chip mounting region.

10 . The COF package of claim 3 , further comprising:
a plurality of outer output conductive patterns formed on the top surface of the base film and respectively connected to chip outer output pads formed on the bottom surface of the semiconductor chip; wherein the outer output conductive patterns include: a plurality of top outer output pads arranged along the first direction within the output pad region; and a plurality of outer output lead lines respectively connected to the top outer output pads and extended along the second direction across the first long side of the chip mounting region; and wherein the bottom inner output conductive patterns include a plurality of inner output lead lines formed on the bottom surface of the base film and extended along the second direction across the first long side of the chip mounting region, wherein the outer output conductive patterns include the outer output lead lines formed on the top surface of the based film and extended along the second direction across the first long side of the chip mounting region, and wherein the inner output lead lines and the outer output lead lines are arranged alternatively one by one along the first direction.

11 . The COF package of claim 3 , further comprising:
a plurality of top input conductive patterns formed on the top surface of the base film and respectively connected to chip input pads formed on the bottom surface of the semiconductor chip; wherein the top input conductive patterns include: a plurality of top input pads arranged along the first direction within the input pad region; and a plurality of top input lead lines respectively connected to the top input pads and extended along the second direction across the second long side of the chip mounting region.

12 . The COF package of claim 11 , further comprising:
a plurality of bottom input conductive patterns formed on the bottom surface of the base film; and a plurality of input vias formed to penetrate the base film and to connect the top input conductive patterns and the bottom input, respectively, the input vias arranged along the first direction.

13 . The COF package of claim 12 , wherein the bottom input conductive patterns include:
a plurality of bottom input via pads arranged beneath the input vias; and a plurality of bottom input lead lines respectively connected to the bottom input via pads and extended along the second direction.

14 . The COF package of claim 1 , wherein the base film includes a bending region corresponding to an end portion of the base film that is bent such that the bottom surface of the bending region faces upwards.

15 . A display device comprising:
a display panel; and a chip-on-film (COF) package configured to drive the display panel, the COF package comprising:
a base film;
a display driver chip mounted on a chip mounting region of a top surface of the base film;
a plurality of top inner output conductive patterns formed on the top surface of the base film and respectively connected to chip inner output pads formed on a bottom surface of the semiconductor chip;
a plurality of bottom inner output conductive patterns formed on a bottom surface of the base film and connected to the display panel; and
a plurality of landing vias formed to vertically penetrate the base film and to respectively connect the top inner output conductive patterns and the bottom inner output conductive patterns, the landing vias arranged within the chip mounting region to form a two-dimensional shape.

16 . The display device of claim 15 , wherein the COF package further includes:
a plurality of outer output conductive patterns formed on the top surface of the base film and respectively connected to chip outer output pads formed on the bottom surface of the semiconductor chip; and a plurality of top input conductive patterns formed on the top surface of the base film and respectively connected to chip input pads formed on the bottom surface of the semiconductor chip.

17 . A chip-on-film (COF) package comprising:
a base film; a semiconductor chip mounted on a chip mounting region of a top surface of the base film; a plurality of top inner output conductive patterns formed on the top surface of the base film and respectively connected to chip inner output pads formed on a bottom surface of the semiconductor chip; a plurality

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Young-Jin
• Jung Jong-Min
• Hur Yun-Ji
• Park Sung-Sik
• Lee Keun-Bong

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/354

  comprising polymers · CPC title