Thin film transistor and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016204267-A1
Application number	US-201514886214-A
Country	US
Kind code	A1
Filing date	Oct 19, 2015
Priority date	Jan 12, 2015
Publication date	Jul 14, 2016
Grant date	—

Abstract

Provided is a thin film transistor (TFT) that includes a first electrode on a substrate separated from a second electrode, an oxide semiconductor pattern on the second electrode including a channel region, a third electrode on the oxide semiconductor pattern, a first insulating layer on the substrate including the third electrode including first contact holes exposing a part of the first electrode, a part of the second electrode, and a part of the third electrode, a gate electrode on the first insulating layer and corresponding to a part of the oxide semiconductor pattern, a second insulating layer on the substrate including the gate electrode including a second contact hole corresponding to the first contact hole that exposes a part of the second electrode, and a pixel electrode on the second insulating layer electrically connected to the second electrode through the first contact hole and the second contact hole.

First claim

What is claimed is:

1 . A thin film transistor (TFT) comprising:
a first electrode positioned on a substrate and a second electrode separated from the first electrode; an oxide semiconductor pattern positioned on the second electrode and including a channel region; a third electrode positioned on the oxide semiconductor pattern; a first insulating layer positioned on the substrate including the third electrode and including first contact holes exposing a part of the first electrode, a part of the second electrode, and a part of the third electrode; a gate electrode positioned on the first insulating layer and corresponding to a part of the oxide semiconductor pattern; a second insulating layer positioned on the substrate including the gate electrode and including a second contact hole corresponding to the first contact hole that exposes a part of the second electrode; and a pixel electrode positioned on the second insulating layer and electrically connected to the second electrode through one of the first contact holes and through the second contact hole.

2 . The TFT of claim 1 , wherein the second electrode is positioned under the oxide semiconductor pattern and the third electrode is positioned on the oxide semiconductor pattern to form a stacked structure.

3 . The TFT of claim 1 , wherein the second electrode and the third electrode comprise different metal materials from each other.

4 . The TFT of claim 1 , wherein the oxide semiconductor pattern comprises indium-tin-zinc-oxide (ITZO).

5 . The TFT of claim 1 , further comprising a connection pattern positioned on the first insulating layer to electrically connect the first electrode and the third electrode through the first contact hole.

6 . The TFT of claim 5 , wherein the connection pattern comprises the same material as the gate electrode in the same layer as the gate electrode.

7 . The TFT of claim 1 , wherein the first electrode comprises the same material as the second electrode in the same layer as the second electrode.

8 . A method of manufacturing a thin film transistor (TFT), the method comprising:
forming a first electrode and a second electrode separated from the first electrode on a substrate; forming an oxide semiconductor pattern including a channel region on the second electrode; forming a third electrode that overlaps a part of the second electrode on the oxide semiconductor pattern; forming a first insulating layer including first contact holes exposing a part of the first electrode, a part of the second electrode, and a part of the third electrode on the substrate including the third electrode; forming a connection pattern for electrically connecting the first electrode and the third electrode through the first contact hole at the same time when a gate electrode corresponding to a part of the oxide semiconductor pattern is formed on the first insulating layer; forming a second insulating layer including a second contact hole corresponding to the first contact hole that exposes a part of the second electrode on the gate electrode; and forming a pixel electrode electrically connected to the second electrode through the first contact hole and the second contact hole on the second insulating layer.

9 . The method of claim 8 , wherein the second electrode is positioned under the oxide semiconductor pattern and the third electrode is positioned on the oxide semiconductor pattern to form a stacked structure.

10 . The method of claim 8 , wherein the second electrode and the third electrode comprise different metal materials from each other.

11 . The method of claim 8 , wherein the channel region is determined by a region caused by offset between the third electrode and the oxide semiconductor pattern and a thickness of the oxide semiconductor pattern.

12 . The method of claim 8 , wherein the oxide semiconductor pattern comprises indium-tin-zinc-oxide (ITZO).

13 . A method of manufacturing a thin film transistor (TFT), the method comprising:
subsequently forming a conductive layer and an oxide semiconductor layer on a substrate; after depositing a photoresist layer on the oxide semiconductor layer, arranging a mask on the photoresist layer to form a first photoresist layer pattern and a second photoresist layer pattern thicker than the first photoresist layer pattern; etching exposed parts of the oxide semiconductor layer and the conductive layer by using the first photoresist layer pattern and the second photoresist layer pattern as masks to form an oxide semiconductor pattern, a first electrode, and a second electrode separated from the first electrode by a uniform distance; removing the first photoresist layer pattern to expose the oxide semiconductor pattern to the outside and forming the second photoresist layer pattern to a third photoresist layer pattern having a small thickness; removing the exposed oxide semiconductor pattern and exposing the first electrode and the second electrode positioned under the oxide semiconductor pattern to the outside; removing the third photoresist layer pattern and exposing the second electrode positioned under the third photoresist layer pattern and the oxide semiconductor pattern including a channel region to the outside; forming a third electrode positioned on the oxide semiconductor pattern and overlapping a part of the second electrode; forming a first insulating layer including first contact holes exposing a part of the first electrode, a part of the second electrode, and a part of the third electrode on the third electrode; forming a connection pattern for electrically connecting the first electrode and the third electrode through the first contact hole at the same time when a gate electrode corresponding to a part of the oxide semiconductor pattern is formed on the first insulating layer; forming a second insulating layer including a second contact hole corresponding to the first contact hole that exposes a part of the second electrode on the gate electrode; and forming a pixel electrode electrically connected to the second electrode through the first contact hole and the second contact hole on the second insulating layer.

14 . The method of claim 13 , wherein the second electrode is positioned under the oxide semiconductor pattern and the third electrode is positioned on the oxide semiconductor pattern to form a stacked structure.

15 . The method of claim 13 , wherein the second electrode and the third electrode comprise different metal materials from each other.

16 . The method of claim 13 , wherein the channel region is determined by a region caused by offset between the third electrode and the oxide semiconductor pattern and a thickness of the oxide semiconductor pattern.

17 . The method of claim 13 , wherein the oxide semiconductor pattern comprises indium-tin-zinc-oxide (ITZO).

18 . A thin film transistor (TFT) comprising:
a source electrode positioned on a substrate; an oxide semiconductor pattern positioned on the source electrode and including a channel region; a drain electrode positioned on the oxide semiconductor pattern; an insulating layer positioned on the substrate including the drain electrode and including contact holes exposing a part of the source electrode and a part of the drain electrode; and a gate electrode positioned on the insulating layer and corresponding to a part of the oxide semiconductor pattern, wherein the source electrode is positioned under the oxide semiconductor pattern and the drain electrode is positioned on the oxide semiconductor pattern

Assignees

• Samsung Display Co Ltd

Inventors

• Moon Yeon-Keon
• Lee Je-Hun

Classifications

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P50/69

  using masks for semiconductor materials · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title