Protection layer on fin of fin field effect transistor (finfet) device structure

Patent metadata

Field	Value
Publication number	US-2016204245-A1
Application number	US-201514677405-A
Country	US
Kind code	A1
Filing date	Apr 2, 2015
Priority date	Jan 12, 2015
Publication date	Jul 14, 2016
Grant date	—

Abstract

A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.

First claim

1 . A fin field effect transistor (FinFET) device structure, comprising:
a substrate; a fin structure extending from the substrate; an isolation structure formed on the substrate, wherein the fin structure has a top portion and a bottom portion, the bottom portion is embedded in the isolation structure; a protection layer formed on the top portion of the fin structure, wherein an interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm; and a source/drain (S/D) structure formed on and in direct contact with a portion of the protection layer, wherein a top surface of the S/D structure is higher than a top surface of the protection layer.

2 . The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the protection layer is made of silicon oxide, silicon oxynitride, silicon oxycarbide (SiOC) or combinations thereof.

3 . (canceled)

4 . The fin field effect transistor (FinFET) device structure as claimed in claim 1 , further comprising:
a gate structure formed on a middle portion of the fin structure, wherein the protection layer is formed between the fin structure and the gate structure.

5 . The fin field effect transistor (FinFET) device structure as claimed in claim 4 , wherein the middle portion of the fin structure is a channel region, and the channel region is wrapped by the protection layer.

6 . The fin field effect transistor (FinFET) device structure as claimed in claim 4 wherein the source/drain (S/D) structure adjacent to the gate structure, wherein the protection layer is formed between the S/D structure and the fin structure.

7 . The fin field effect transistor (FinFET) device structure as claimed in claim 6 , wherein the S/D structure comprises silicon germanium (SiGe), germanium (Ge), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium arsenide (GaAs), gallium antimonide (GaSb), indium aluminum phosphide (InAlP), indium phosphide (InP), or a combination thereof.

8 . The fin field effect transistor (FinFET) device structure as claimed in claim 1 , further comprising:
an inter-layer dielectric (ILD) structure formed on the isolation structure, wherein a portion of the protection layer is formed between the ILD structure and the fin structure.

9 . A fin field effect transistor (FinFET) device structure, comprising:
a substrate; a fin structure formed on the substrate; a gate structure formed on a middle portion of the fin structure, wherein the gate structure comprises a high-k dielectric layer and a metal gate electrode layer formed on the high-k dielectric layer; a protection layer formed between the fin structure and the high-k dielectric layer; and a source/drain (S/D) structure formed on and in direct contact with a portion of the protection layer, wherein a top surface of the S/D structure is higher than a top surface of the protection layer.

10 . The fin field effect transistor (FinFET) device structure as claimed in claim 9 , wherein an interface is between the protection layer and the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.

11 . The fin field effect transistor (FinFET) device structure as claimed in claim 9 ,
wherein the source/drain (S/D) structure adjacent to the gate structure, wherein the protection layer is formed between the S/D structure and the fin structure.

12 . The fin field effect transistor (FinFET) device structure as claimed in claim 9 , further comprising:
an inter-layer dielectric (ILD) structure formed on the fin structure, wherein a portion of the protection layer is formed between the ILD structure and the fin structure.

13 . A method for forming a fin field effect transistor (FinFET) device structure, comprising:
providing a substrate; forming a fin structure on the substrate; forming an isolation structure on the substrate, wherein the fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure; forming a protection layer on the top portion of the fin structure, wherein an interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm; and forming a source/drain (S/D) structure on and in direct contact with a portion of the protection layer, wherein a top surface of the S/D structure is higher than a top surface of the protection layer.

14 . The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 13 , wherein forming the protection layer comprises using a microwave plasma process, a thermal oxidation process, a plasma-enhanced chemical vapor deposition process (PECVD) process, or atomic layer deposition (ALD) process.

15 . The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 14 , wherein defects or the dangling bonds in the top portion of the fin structure are repaired by the microwave plasma process.

16 . The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 14 , wherein the microwave plasma process is performed by using oxygen gas (O 2 ), hydrogen (H 2 ) gas or combinations thereof.

17 . The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 14 , wherein the microwave plasma process is performed at a temperature in a range from about 400 degrees to about 600 degrees.

18 . The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 14 , wherein the microwave plasma process is performed under a pressure in a range from about 0.1 torr to about 10 torr.

19 . The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 13 , further comprising:
before forming the isolation structure on the substrate, forming a dielectric layer on the fin structure and the substrate; forming a sacrificial layer on the fin structure and the dielectric layer; doping the fin structure; removing the sacrificial layer; and removing the top portion of the dielectric layer to expose the top portion of the fin structure.

20 . (canceled)

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Jangjian Shiu-Ko
• Jeng Chi-Cherng
• Wu Chih-Nan
• Lin Chun-Che
• Wang Ting-Chun

Classifications

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/832

  being Group IV materials comprising two or more elements, e.g. SiGe · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title