Gate dielectric protection for transistors

Patent metadata

Field	Value
Publication number	US-2016204098-A1
Application number	US-201615080090-A
Country	US
Kind code	A1
Filing date	Mar 24, 2016
Priority date	Jul 1, 2014
Publication date	Jul 14, 2016
Grant date	—

Abstract

At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge.

First claim

1 . A method for forming a transistor, comprising:
forming a source region on a substrate; forming an active gate region on said substrate adjacent said source region; forming a drain region on said substrate adjacent said active gate region; and forming a first inactive gate region on said substrate in parallel to said active gate region, wherein said source region, said drain region, said active gate region, and said first inactive gate region comprise said transistor, and wherein said first inactive gate region is capable of dissipating at least a portion of a charge.

2 . The method of claim 1 , wherein said first inactive gate region is further capable of at least partially dissipating said charge resulting from a plasma process.

3 .- 8 . (canceled)

9 . The method of claim 1 , further comprising forming a second inactive gate region on said substrate in parallel to first inactive gate, wherein said second inactive gate is capable of at dissipating said at least a portion of said charge.

10 . (canceled)

11 . An integrated circuit device, comprising:
a transistor, comprising:
a source region on a substrate;
an active gate region on said substrate adjacent said source region;
a drain region on said substrate adjacent said active gate region; and
an inactive gate region on said substrate in parallel to said active gate region, wherein said inactive gate region is capable of dissipating at least a portion of a charge.

12 . The integrated circuit device of claim 11 , wherein said charge is at least one of a leaked charge from a plasma process, or a charge from an external electrical field.

13 .- 16 . (canceled)

17 . A system, comprising:
a semiconductor device processing system to provide a device comprising at least one transistor, wherein said transistor comprises;
a source region on a substrate;
an active gate region on said substrate adjacent said source region;
a drain region on said substrate adjacent said active gate region; and
an inactive gate region on said substrate in parallel to said active gate region, wherein said inactive gate region is capable of dissipating said at least a portion of a charge; and
a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of said semiconductor device processing system.

18 . The system of claim 17 , further comprising:
a testing module for testing said transistor, wherein said testing module is capable of providing an indication of a current leakage in said transistor; an inactive gate unit to determine the number of inactive gate regions to form based upon at least one of said indication of said current leakage, or a predetermine antenna ratio.

19 . The system of claim 17 , wherein said processing controller is capable of controlling the number of inactive gates that are formed in a subsequent device formed by said semiconductor device processing system based upon at least one of data from said testing module, or data from said inactive gate unit.

20 . The system of claim 17 , wherein said device is at least one of a CMOS device, a BiCMOS device, a Flash device, a DRAM memory device, and a power device.

21 . The system of claim 17 , wherein said active gate comprises a plurality of gates stacked vertically and separated by a dielectric layer.

Assignees

• Globalfoundries Inc

Inventors

• Kerber Andreas
• Uppal Suresh
• Cimino Salvatore
• Jiang Hao

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/27

  Structural arrangements therefor · CPC title

• H10D64/01306

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title